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2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)最新文献

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A self biased operational amplifier at ultra low power supply voltage 超低电源电压下的自偏置运算放大器
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410958
G. Praneeth, Anil K. Saini
{"title":"A self biased operational amplifier at ultra low power supply voltage","authors":"G. Praneeth, Anil K. Saini","doi":"10.1109/ICECS.2009.5410958","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410958","url":null,"abstract":"This paper discusses the design of a self-biased folded cascode operational amplifier at an ultra low power supply voltage. The proposed design is first of its kind at 0.5 V where self-biasing techniques are used to reduce power and area overheads. The self-biasing scheme in this design is developed by using a current mirror for low voltage operation. This design is implemented in a 90 nm CMOS technology using Cadence General Purpose Design Kit (GPDK).","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131969172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Exploitation of the phasor approach for closed-form solution of the Van der Pol's oscillator and sinusoidal oscillators with high-order nonlinearity 具有高阶非线性的Van der Pol振子和正弦振子闭型解的相量法
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410963
G. Palumbo, M. Pennisi, S. Pennisi
{"title":"Exploitation of the phasor approach for closed-form solution of the Van der Pol's oscillator and sinusoidal oscillators with high-order nonlinearity","authors":"G. Palumbo, M. Pennisi, S. Pennisi","doi":"10.1109/ICECS.2009.5410963","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410963","url":null,"abstract":"In this paper the phasor approach is applied to find the solution of the well-known Van der Pol's equation for both quasi-sinusoidal and relaxation oscillation regimes. It allows to find simple closed-form relationships for the output harmonics of a LC oscillator whose behavior is described by the Van der Pol's equation. Furthermore, the validity of the phasor approach is extended to analyze also oscillators with nonlinearity of order higher than three. As an example a LC oscillator with a polynomial nonlinearity of fifth order is considered and closed-form relationships for the output harmonics are found. The analysis developed, both for the Van der Pol's equation and for oscillators with high-order nonlinearity, is verified by means of simulations performed with Spectre.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131978851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficienct LED driver with an adaptive reference tracking technique 高效的LED驱动器与自适应参考跟踪技术
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410997
C. Hsieh, Young-Sheng Wei, Ke-Horng Chen, Tseng-Chun Lin
{"title":"Efficienct LED driver with an adaptive reference tracking technique","authors":"C. Hsieh, Young-Sheng Wei, Ke-Horng Chen, Tseng-Chun Lin","doi":"10.1109/ICECS.2009.5410997","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410997","url":null,"abstract":"An adaptive reference tracking driving technique is proposed to minimize the boost output voltage oscillation and improve the power efficiency when the digital pulse width modulation dimming is enabled. An asynchronous 1MHz DC/DC converter with a dynamic resistor implements the minimum voltage reference tracking technique. Therefore, high efficiency and a stable boost output voltage can be guaranteed whether the LED strings turn on or off. The test chip was simulated by TSMC 0.25um BCD 40V to demonstrate high efficiency and the stable boost output voltage. Simulation results show the oscillation output voltage can be minimized from 1.4V to 0.2V.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"324 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132420421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Clock recovery for a 40 Gb/s QPSK optical receiver 40gb /s QPSK光接收机的时钟恢复
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410782
Naim Ben-Hamida, J. Sitch, Philip Flemke, D. Pollex, P. Schvan, Y. Greshishchev, Shing-Chi Wang, C. Falt
{"title":"Clock recovery for a 40 Gb/s QPSK optical receiver","authors":"Naim Ben-Hamida, J. Sitch, Philip Flemke, D. Pollex, P. Schvan, Y. Greshishchev, Shing-Chi Wang, C. Falt","doi":"10.1109/ICECS.2009.5410782","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410782","url":null,"abstract":"A clock recovery circuit for a 40Gb/s optical coherent receiver realized in CMOS 90nm technology is presented. The core PLL generates less 0.3ps rms jitter for a bandwidth of 0.5MHz. This is mainly due to the on-chip differential LC VCO with power supply regulation. The VCO operates at 11.5GHz center frequency with a 25% tuning range. Its phase noise at 1MHz offset is better than −110dBc/Hz, and consumes 3mW of power. In tone acquisition mode the PLL is a regular charge pump PLL, while in data acquisition mode the DSP core corrects the frequency through the tuning ports. The presented PLL is one of the key components in the 24Gs/s ADC and coherent receiver chip.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134203008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Application of MO-TRIBES to the design of analog electronic circuits MO-TRIBES在模拟电子电路设计中的应用
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410986
Y. Cooren, P. Siarry, M. Fakhfakh
{"title":"Application of MO-TRIBES to the design of analog electronic circuits","authors":"Y. Cooren, P. Siarry, M. Fakhfakh","doi":"10.1109/ICECS.2009.5410986","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410986","url":null,"abstract":"This paper deals with using MO-TRIBES, an adaptive multiobjective Particle Swarm Optimization algorithm, for optimally sizing CMOS positive second generation Current Conveyors. Pareto front is generated while minimizing parasitic X-port input resistance RX and maximizing current high cut-off frequency fchi. Results obtained using MO-TRIBES are provided and compared to those obtained using the classical MOPSO algorithm. SPICE simulation results are presented to validate obtained sizing.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"54 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131626789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A novel CMOS all-pass tunable phase shifter 一种新型CMOS全通可调移相器
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410888
A. Mohammadi, A. Abrishamifar, A. Ayatollahi
{"title":"A novel CMOS all-pass tunable phase shifter","authors":"A. Mohammadi, A. Abrishamifar, A. Ayatollahi","doi":"10.1109/ICECS.2009.5410888","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410888","url":null,"abstract":"A new current mirror based all-pass, tunable phase shifting technique is proposed and simulated in 0.18um CMOS, after a brief introduction on phase shifter applications, and comparison between different implementation methods. In the new current-mode approach, cut-off frequency of transistor is the operational limit of the proposed phase-shifter architecture and power consumption for this design is 80 microwatts. Simulations are carried out in HSpice and cover a frequency range from 0.1GHz to 50 GHz.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132804759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Analysis of the impact of random process variations in CMOS tapered buffers 随机工艺变化对CMOS锥形缓冲器的影响分析
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410918
M. Alioto, G. Palumbo, M. Pennisi
{"title":"Analysis of the impact of random process variations in CMOS tapered buffers","authors":"M. Alioto, G. Palumbo, M. Pennisi","doi":"10.1109/ICECS.2009.5410918","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410918","url":null,"abstract":"In this paper, the effect of intradie process variations on the delay of tapered buffers designed in static CMOS logic style is analyzed in depth. An analytical delay model accounting for the dependency of variations on transistor sizing, load and input capacitance requirement is derived for the single stage. Then, this model is extended to the case of N-stage tapered buffers. The closed-form delay expressions including the contribution of intradie variations permit to gain an insight into the impact of process variations on the performance of tapered buffers. Monte Carlo simulations on a 90-nm technology including layout parasitics are performed to validate the analysis. Results are shown to agree well with the expressions derived, thereby confirming the validity of the underlying assumptions, as well as the suitability of the proposed models for design purposes.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131075616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A low-dropout regulator with smooth peak current control (SPCC) topology for over current protection 具有平滑峰值电流控制(SPCC)拓扑的低压差稳压器，用于过电流保护
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410917
C. Hsieh, Chih-Yu Yang, Ke-Horng Chen
{"title":"A low-dropout regulator with smooth peak current control (SPCC) topology for over current protection","authors":"C. Hsieh, Chih-Yu Yang, Ke-Horng Chen","doi":"10.1109/ICECS.2009.5410917","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410917","url":null,"abstract":"The proposed LDO regulator with a smooth peak current control (SPCC) circuit can be simultaneously controlled by an error amplifier to regulate the output voltage and the peak current controller to limit the current level. The SPCC circuit detects the information of load current and the dropout voltage to smoothly switch between the error amplifier and the peak current controller. The experimental results show that when the load current exceed the peak current level, the over current protection can make the pass device operate as a current source to prevent the over current damaging the chip. Moreover, the control mechanism can return back to error amplifier control when load current becomes smaller than the limiting current and the output voltage close to the rated value for avoiding the oscillator. The output voltage is stable and varies smaller than 15 mV when a 160 mA load current step or a 2 V supply voltage step is put on this LDO regulator.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"185 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133586753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A design methodology for high-performance and low-leakage fixed-point transpose FIR filters 一种高性能低漏定点转置FIR滤波器的设计方法
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410902
D. Bekiaris, S. Xydis, G. Economakos, K. Pekmestzi
{"title":"A design methodology for high-performance and low-leakage fixed-point transpose FIR filters","authors":"D. Bekiaris, S. Xydis, G. Economakos, K. Pekmestzi","doi":"10.1109/ICECS.2009.5410902","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410902","url":null,"abstract":"This paper addresses the low leakage implementation of fixed-point transpose FIR filters, considering dual-Vth CMOS standard-cell libraries. Specifically, we introduce a design flow, based on a novel two-level selection algorithm, which replaces low-Vth Multiplication-Addition units by their high-Vth counterparts, taking into account the timing slack of each unit and the word-level binary representation of the units' coefficients. The proposed methodology is evaluated on an 8-tap and a 16-tap transpose FIR filters. Post-layout power results demonstrate leakage improvements ranging from 6.69–25.85% for several clock period constraints, compared to the low-Vth FIR implementations. Also, reduction of up to 12.35% is measured in overall power dissipation.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127855041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A dilated LMI approach to robust H∞ static state feedback controller synthesis 鲁棒H∞静态反馈控制器综合的扩展LMI方法
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410885
Kamel Dabboussi, J. Zrida
{"title":"A dilated LMI approach to robust H∞ static state feedback controller synthesis","authors":"Kamel Dabboussi, J. Zrida","doi":"10.1109/ICECS.2009.5410885","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410885","url":null,"abstract":"This paper introduces a dilated Linear Matrix Inequality (LMI) approach to the robust H∞ analysis for linear continuous-time uncertain systems. This approach has the interesting property that it provides LMI conditions in which the state matrix is separated from the Lyapunov variable. In addition, it is also shown, in this paper, that the obtained dilated LMI conditions always encompass the quadratic ones. Altogether, these facts will guarantee that the provided solutions will be, at worst, as good as the ones obtained by the quadratic approach. These results are shown to also hold for the robust H∞ state-feedback control synthesis problem. A numerical example is presented to illustrate the advantages of the proposed method.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131295088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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