超低电源电压下的自偏置运算放大器

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI:10.1109/ICECS.2009.5410958

G. Praneeth, Anil K. Saini

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引用次数: 6

摘要

本文讨论了一种超低电源电压下自偏置折叠级联码运算放大器的设计。提出的设计是同类中第一个在0.5 V下使用自偏置技术来降低功率和面积开销的设计。本设计的自偏置方案是利用电流反射镜进行低电压工作。本设计使用Cadence通用设计套件(GPDK)在90纳米CMOS技术中实现。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A self biased operational amplifier at ultra low power supply voltage

This paper discusses the design of a self-biased folded cascode operational amplifier at an ultra low power supply voltage. The proposed design is first of its kind at 0.5 V where self-biasing techniques are used to reduce power and area overheads. The self-biasing scheme in this design is developed by using a current mirror for low voltage operation. This design is implemented in a 90 nm CMOS technology using Cadence General Purpose Design Kit (GPDK).

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来源期刊

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)

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