Analysis of the impact of random process variations in CMOS tapered buffers

Abstract

In this paper, the effect of intradie process variations on the delay of tapered buffers designed in static CMOS logic style is analyzed in depth. An analytical delay model accounting for the dependency of variations on transistor sizing, load and input capacitance requirement is derived for the single stage. Then, this model is extended to the case of N-stage tapered buffers. The closed-form delay expressions including the contribution of intradie variations permit to gain an insight into the impact of process variations on the performance of tapered buffers. Monte Carlo simulations on a 90-nm technology including layout parasitics are performed to validate the analysis. Results are shown to agree well with the expressions derived, thereby confirming the validity of the underlying assumptions, as well as the suitability of the proposed models for design purposes.