D. Bekiaris, S. Xydis, G. Economakos, K. Pekmestzi
{"title":"一种高性能低漏定点转置FIR滤波器的设计方法","authors":"D. Bekiaris, S. Xydis, G. Economakos, K. Pekmestzi","doi":"10.1109/ICECS.2009.5410902","DOIUrl":null,"url":null,"abstract":"This paper addresses the low leakage implementation of fixed-point transpose FIR filters, considering dual-Vth CMOS standard-cell libraries. Specifically, we introduce a design flow, based on a novel two-level selection algorithm, which replaces low-Vth Multiplication-Addition units by their high-Vth counterparts, taking into account the timing slack of each unit and the word-level binary representation of the units' coefficients. The proposed methodology is evaluated on an 8-tap and a 16-tap transpose FIR filters. Post-layout power results demonstrate leakage improvements ranging from 6.69–25.85% for several clock period constraints, compared to the low-Vth FIR implementations. Also, reduction of up to 12.35% is measured in overall power dissipation.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A design methodology for high-performance and low-leakage fixed-point transpose FIR filters\",\"authors\":\"D. Bekiaris, S. Xydis, G. Economakos, K. Pekmestzi\",\"doi\":\"10.1109/ICECS.2009.5410902\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper addresses the low leakage implementation of fixed-point transpose FIR filters, considering dual-Vth CMOS standard-cell libraries. Specifically, we introduce a design flow, based on a novel two-level selection algorithm, which replaces low-Vth Multiplication-Addition units by their high-Vth counterparts, taking into account the timing slack of each unit and the word-level binary representation of the units' coefficients. The proposed methodology is evaluated on an 8-tap and a 16-tap transpose FIR filters. Post-layout power results demonstrate leakage improvements ranging from 6.69–25.85% for several clock period constraints, compared to the low-Vth FIR implementations. Also, reduction of up to 12.35% is measured in overall power dissipation.\",\"PeriodicalId\":343974,\"journal\":{\"name\":\"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2009.5410902\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2009.5410902","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A design methodology for high-performance and low-leakage fixed-point transpose FIR filters
This paper addresses the low leakage implementation of fixed-point transpose FIR filters, considering dual-Vth CMOS standard-cell libraries. Specifically, we introduce a design flow, based on a novel two-level selection algorithm, which replaces low-Vth Multiplication-Addition units by their high-Vth counterparts, taking into account the timing slack of each unit and the word-level binary representation of the units' coefficients. The proposed methodology is evaluated on an 8-tap and a 16-tap transpose FIR filters. Post-layout power results demonstrate leakage improvements ranging from 6.69–25.85% for several clock period constraints, compared to the low-Vth FIR implementations. Also, reduction of up to 12.35% is measured in overall power dissipation.