一种高性能低漏定点转置FIR滤波器的设计方法

D. Bekiaris, S. Xydis, G. Economakos, K. Pekmestzi
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引用次数: 0

摘要

考虑到双vth CMOS标准单元库,本文讨论了定点转置FIR滤波器的低泄漏实现。具体来说,我们介绍了一种基于新颖的两级选择算法的设计流程,该算法将低v值的乘法-加法单元替换为高v值的乘法-加法单元,同时考虑到每个单元的时间松弛和单元系数的词级二进制表示。提出的方法是评估一个8抽头和16抽头转置FIR滤波器。布局后的功率结果表明,与低电压FIR实现相比,在几个时钟周期限制下,泄漏改善范围为6.69-25.85%。此外,总体功耗降低高达12.35%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A design methodology for high-performance and low-leakage fixed-point transpose FIR filters
This paper addresses the low leakage implementation of fixed-point transpose FIR filters, considering dual-Vth CMOS standard-cell libraries. Specifically, we introduce a design flow, based on a novel two-level selection algorithm, which replaces low-Vth Multiplication-Addition units by their high-Vth counterparts, taking into account the timing slack of each unit and the word-level binary representation of the units' coefficients. The proposed methodology is evaluated on an 8-tap and a 16-tap transpose FIR filters. Post-layout power results demonstrate leakage improvements ranging from 6.69–25.85% for several clock period constraints, compared to the low-Vth FIR implementations. Also, reduction of up to 12.35% is measured in overall power dissipation.
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