Clock recovery for a 40 Gb/s QPSK optical receiver

A clock recovery circuit for a 40Gb/s optical coherent receiver realized in CMOS 90nm technology is presented. The core PLL generates less 0.3ps rms jitter for a bandwidth of 0.5MHz. This is mainly due to the on-chip differential LC VCO with power supply regulation. The VCO operates at 11.5GHz center frequency with a 25% tuning range. Its phase noise at 1MHz offset is better than −110dBc/Hz, and consumes 3mW of power. In tone acquisition mode the PLL is a regular charge pump PLL, while in data acquisition mode the DSP core corrects the frequency through the tuning ports. The presented PLL is one of the key components in the 24Gs/s ADC and coherent receiver chip.