2012 IEEE International Reliability Physics Symposium (IRPS)最新文献_第2页

Grain structure analysis and implications on electromigration reliability for Cu interconnects 铜互连线的晶粒结构分析及其电迁移可靠性

2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241896

L. Cao, K. Ganesh, L. Zhang, P. Ferreira, P. Ho

引用次数: 1

Role of grain boundary percolative defects and localized trap generation on the reliability statistics of high-κ gate dielectric stacks 晶界渗透缺陷和局域陷阱产生对高κ栅介电堆可靠性统计的影响

2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241862

N. Raghavan, K. Pey, K. Shubhakar, X. Wu, W. H. Liu, M. Bosman

{"title":"Role of grain boundary percolative defects and localized trap generation on the reliability statistics of high-κ gate dielectric stacks","authors":"N. Raghavan, K. Pey, K. Shubhakar, X. Wu, W. H. Liu, M. Bosman","doi":"10.1109/IRPS.2012.6241862","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241862","url":null,"abstract":"Grain boundary (GB) microstructural defects in polycrystalline high-? dielectric thin films may cause localized non-random trap generation during the percolation breakdown (BD) process. We study the effect of this non-random trap generation on the reliability statistics of the metal gate (MG) - high-κ (HK) stack. For the first time, we propose a fundamental physics-based Kinetic Monte Carlo (KMC) model considering the thermodynamics and kinetics of bond breaking, generation of oxygen vacancy traps and simulating the trap evolution process in a dual-layer HK - interfacial layer (IL) gate stack. Our simulation model helps explain the non-Weibull distribution trends for time dependent dielectric breakdown data (TDDB) and also determine the sequence of BD which is found to be independent of the thickness ratio of (tHK : tIL) and gate voltage (Vg). Results show that the IL layer is always more susceptible to early percolation and circuit level failure may only be caused by multiple soft BD (SBD) events in the IL layer. The possibility of a sequential IL → HK breakdown is very unlikely for operating voltage conditions of Vop = 1V.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"188 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126791043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 23

Hot carrier degradation: From defect creation modeling to their impact on NMOS parameters 热载流子退化:从缺陷产生建模到它们对NMOS参数的影响

2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241945

Y. M. Randriamihaja, A. Zaka, V. Huard, M. Rafik, D. Rideau, D. Roy, A. Bravaix, P. Palestri

引用次数: 16

Reliability of porous low-k dielectrics under dynamic voltage stressing 动态电压应力作用下多孔低k介电材料的可靠性

2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241801

Shou-Chung Lee, A. Oates

引用次数: 7

Gate dielectric TDDB characterizations of advanced High-k and metal-gate CMOS logic transistor technology 栅极电介质TDDB特性的先进高k和金属栅极CMOS逻辑晶体管技术

2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241848

S. Pae, C. Prasad, S. Ramey, J. Thomas, A. Rahman, R. Lu, J. Hicks, S. Batzer, Q. Zhao, J. Hatfield, M. Liu, C. Parker, B. Woolery

引用次数: 17

Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues 新出现的中线多栅-扩散接触可靠性问题的研究

2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241865

Fen Chen, S. Mittl, M. Shinosky, A. Swift, R. Kontra, B. Anderson, J. Aitken, Yanfeng Wang, E. Kinser, M. Kumar, Y. Wang, T. Kane, K. Feng, W. Henson, D. Mocuta, Di-An Li

{"title":"Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues","authors":"Fen Chen, S. Mittl, M. Shinosky, A. Swift, R. Kontra, B. Anderson, J. Aitken, Yanfeng Wang, E. Kinser, M. Kumar, Y. Wang, T. Kane, K. Feng, W. Henson, D. Mocuta, Di-An Li","doi":"10.1109/IRPS.2012.6241865","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241865","url":null,"abstract":"The minimum insulator spacing between the polysilicon control gate (PC) and the diffusion contacts (CA) in advanced VLSI circuits is aggressively shrinking due to continuous technology scaling. Meanwhile, rapid adoptions of new materials such as metal gate, epitaxial SiGe source /drain, stress liner, and copper contact together with new device configurations such as raised source/drain and FinFET may further exacerbate the PC-CA dielectric reliability. SRAM yield loss and functional stress failures of both SRAM and DRAM chips due to middle-of-line (MOL) PC-CA shorts and early breakdown have been observed during the course of technology development at 32nm. Therefore, the leakage and breakdown of middle-of-line (MOL) PC-to-CA dielectric is rapidly becoming an emerging reliability issue for a successful technology development. In this paper, a comprehensive investigation of MOL PC-to-CA reliability issues at 32nm technology node was conducted. A new qualification methodology was developed to assure PC-to-CA reliability at an acceptable level.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124110130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 31

ESD protection structure with inductor-triggered SCR for RF applications in 65-nm CMOS process 具有电感触发可控硅的ESD保护结构，用于65纳米CMOS工艺的射频应用

2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241893

Chun-Yu Lin, Li-Wei Chu, M. Ker, Ming-Hsiang Song, C. Jou, T. Lu, J. Tseng, M. Tsai, T. Hsu, P. Hung, T. Chang

引用次数: 7

The relevance of deeply-scaled FET threshold voltage shifts for operation lifetimes 深度缩放场效应管阈值电压漂移与工作寿命的相关性

2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241839

B. Kaczer, J. Franco, M. Toledano-Luque, P. Roussel, M. Bukhori, A. Asenov, B. Schwarz, M. Bina, T. Grasser, G. Groeseneken

引用次数: 42

Impact of VLSI technology scaling on HTOL VLSI技术规模对HTOL的影响

2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241850

R. Kwasnick, M. Reilly, J. Hatfield, S. C. Johnson, A. Rahman

引用次数: 9

Backend dielectric chip reliability simulator for complex interconnect geometries 用于复杂互连几何形状的后端介电芯片可靠性模拟器

2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241878

Chang-Chih Chen, M. Bashir, L. Milor, Daehyun Kim, S. Lim

引用次数: 12