Gate dielectric TDDB characterizations of advanced High-k and metal-gate CMOS logic transistor technology

S. Pae, C. Prasad, S. Ramey, J. Thomas, A. Rahman, R. Lu, J. Hicks, S. Batzer, Q. Zhao, J. Hatfield, M. Liu, C. Parker, B. Woolery
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引用次数: 17

Abstract

Transition into High-K (HK) dielectric and Metal-Gate (MG) in advanced logic process has enabled continued technology scaling in support of Moore's law [1-2]. With this, CMOS operating fields have been increasing along with gate dielectric TDDB voltage acceleration factors (VAF). VAF is the most critical reliability parameter used to accurately predict the Gate oxide lifetime (TDDB) at use. This paper highlights low voltage (low-V) TDDB data is critical for the accurate assessment of HK+MG VAF and provides further evidences from both transistor- and product-level data based on 32nm technology generations.
栅极电介质TDDB特性的先进高k和金属栅极CMOS逻辑晶体管技术
在先进的逻辑过程中过渡到高k (HK)电介质和金属栅极(MG)使技术持续缩放以支持摩尔定律[1-2]。因此,CMOS工作场随着栅极介质TDDB电压加速因子(VAF)的增大而增大。VAF是用于准确预测栅极氧化物寿命(TDDB)的最关键的可靠性参数。本文强调了低电压(low- v) TDDB数据对于准确评估HK+MG VAF至关重要,并提供了基于32纳米技术世代的晶体管和产品级数据的进一步证据。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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