发布求助
文献互助 智能选刊 最新文献

2012 IEEE International Reliability Physics Symposium (IRPS)最新文献

筛选
英文 中文
Multi-technique study of defect generation in high-k gate stacks 高k栅极堆缺陷产生的多技术研究
2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241853
D. Veksler, G. Bersuker, H. Madan, L. Vandelli, M. Minakais, K. Matthews, C. Young, S. Datta, C. Hobbs, P. Kirsch
{"title":"Multi-technique study of defect generation in high-k gate stacks","authors":"D. Veksler, G. Bersuker, H. Madan, L. Vandelli, M. Minakais, K. Matthews, C. Young, S. Datta, C. Hobbs, P. Kirsch","doi":"10.1109/IRPS.2012.6241853","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241853","url":null,"abstract":"A set of measurement techniques- SILC, low frequency noise, and pulse CV - combined with the physical descriptions of the processes associated with these measurements were applied to study pre-existing and stress generated traps in the SiO2/HfO2 gate stacks. By correlating the analysis results obtained by these techniques, the defects in the high-k dielectric and interfacial layer were identified. The stress-induced degradation of the high-k gate stack was found to be caused primarily by the trap generation in the SiO2 interfacial layer.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115693342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Impact of program/erase stress induced hole current on data retention degradation for MONOS memories 程序/擦除应力引起的空穴电流对MONOS存储器数据保留退化的影响
2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241772
S. Fujii, R. Fujitsuka, K. Sekine, H. Kusai, K. Sakuma, M. Koyama
{"title":"Impact of program/erase stress induced hole current on data retention degradation for MONOS memories","authors":"S. Fujii, R. Fujitsuka, K. Sekine, H. Kusai, K. Sakuma, M. Koyama","doi":"10.1109/IRPS.2012.6241772","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241772","url":null,"abstract":"We investigate the mechanism for the data retention degradation caused by program/erase (P/E) cycling in MONOS memories, using the carrier separation measurement to identify the carrier type of Stress-Induced Leakage Current (SILC). It is thereby found that SILC is composed mainly of holes for the MONOS with less Si-rich SiN layer (hole SILC). A clear correlation is also discovered between hole SILC and interface states generated during P/E cycle. We also discuss the mechanism of the degradation by hole SILC of the data retention characteristics of MONOS devices.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115763772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Correlation of single trapping and detrapping effects in drain and gate currents of nanoscaled nFETs and pFETs 纳米nfet和pfet漏极和栅极电流中单捕集和去捕集效应的相关性
2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241935
M. Toledano-Luque, B. Kaczer, E. Simoen, R. Degraeve, J. Franco, P. Roussel, T. Grasser, G. Groeseneken
{"title":"Correlation of single trapping and detrapping effects in drain and gate currents of nanoscaled nFETs and pFETs","authors":"M. Toledano-Luque, B. Kaczer, E. Simoen, R. Degraeve, J. Franco, P. Roussel, T. Grasser, G. Groeseneken","doi":"10.1109/IRPS.2012.6241935","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241935","url":null,"abstract":"The correlation of discrete gate and drain current fluctuations is revealed in nanoscaled SiON pFETs and nFETs, demonstrating that discrete trapping and detrapping events in the same single states are responsible of both ID and IG random telegraph noise (RTN). The high and low gate current IG-RTN levels are independent of temperature but the switching rates thermally activated indicating that the trapping and detrapping events are consistent with nonradiative multiphonon theory.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117219265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
Burn-in stress induced BTI degradation and post-burn-in high temperature anneal (Bake) effects in advanced HKMG and oxynitride based CMOS ring oscillators 在先进的HKMG和氮氧化物基CMOS环形振荡器中，烧坏应力诱导的BTI降解和烧坏后高温退火(Bake)效应
2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241849
D. Ioannou, S. Mittl, D. Brochu
{"title":"Burn-in stress induced BTI degradation and post-burn-in high temperature anneal (Bake) effects in advanced HKMG and oxynitride based CMOS ring oscillators","authors":"D. Ioannou, S. Mittl, D. Brochu","doi":"10.1109/IRPS.2012.6241849","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241849","url":null,"abstract":"The impact of Bias Temperature Instability stress and poststress high temperature anneal (bake) effects on the performance of Ring Oscillator (RO) circuits is investigated for advanced node High-k Metal Gate (HKMG) and Oxynitride (SiON) based Silicon-On-Insulator (SOI) CMOS technologies. Examination of the circuit response (in terms of % frequency degradation) to a wide range of stress bias/temperature conditions reveals a distinct difference between the two technologies with respect to the voltage acceleration of frequency degradation. This difference is explained in view of the PBTI/NBTI voltage acceleration behaviour and indicates that PBTI dominates HKMG RO performance degradation. Post burn-in bake is found to be equally effective in recovering the burn-in induced frequency degradation in both HKMG and Oxynitride ROs. Finally, a simple model is proposed to predict net RO performance degradation from a combined burn-in/post-burn-in bake as a useful guideline for optimizing product burn-in testing.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125003396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Reliability characterization of 32nm high-k metal gate SOI technology with embedded DRAM 嵌入DRAM的32nm高k金属栅极SOI技术的可靠性表征
2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241866
S. Mittl, A. Swift, E. Wu, D. Ioannou, Fen Chen, G. Massey, N. Rahim, M. Hauser, P. Hyde, J. Lukaitis, S. Rauch, S. Saroop, Yanfeng Wang
{"title":"Reliability characterization of 32nm high-k metal gate SOI technology with embedded DRAM","authors":"S. Mittl, A. Swift, E. Wu, D. Ioannou, Fen Chen, G. Massey, N. Rahim, M. Hauser, P. Hyde, J. Lukaitis, S. Rauch, S. Saroop, Yanfeng Wang","doi":"10.1109/IRPS.2012.6241866","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241866","url":null,"abstract":"The reliability characterization of a high performance 32nm SOI CMOS technology featuring gate first High-K Metal Gate and embedded High-K Metal Fill DRAM is presented. This technology features high performance 0.9V thin dielectric devices and 1.5V thick dielectric I/O devices. Included are results of Hot Carrier, Bias Temperature, Planar and Trench Node TDDB, Gate to Contact, silicon eFUSE, SER, SRAM and Logic circuit reliability evaluations.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125917467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
28nm node bulk vs FDSOI reliability comparison 28nm节点体与FDSOI可靠性比较
2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241805
X. Federspiel, D. Angot, M. Rafik, F. Cacho, A. Bajolet, N. Planes, D. Roy, M. Haond, F. Arnaud
{"title":"28nm node bulk vs FDSOI reliability comparison","authors":"X. Federspiel, D. Angot, M. Rafik, F. Cacho, A. Bajolet, N. Planes, D. Roy, M. Haond, F. Arnaud","doi":"10.1109/IRPS.2012.6241805","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241805","url":null,"abstract":"In this paper, we present TDDB, HCI and BTI reliability characterization of Nfet and Pfet devices issued from FDSOI and bulk 28nm technologies. 28nm FDSOI devices achieve 32% improved performance, 40% reduced power consumption and improved matching. From device level tests, 28nm FDSOI also demonstrates intrinsic reliability behavior similar to 28 bulk devices, giving confidence in the robustness of this technology.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123297484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
Design and analysis of anchorless shuttle nano-electro-mechanical non-volatile memory for high temperature applications 高温无锚梭型纳米机电非易失性存储器的设计与分析
2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241917
Ramesh Vaddi, T. T. Kim, Vincent Pott, J. T. M. Lin
{"title":"Design and analysis of anchorless shuttle nano-electro-mechanical non-volatile memory for high temperature applications","authors":"Ramesh Vaddi, T. T. Kim, Vincent Pott, J. T. M. Lin","doi":"10.1109/IRPS.2012.6241917","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241917","url":null,"abstract":"This paper presents a novel nano-electro-mechanical (NEM) non-volatile memory (NVM) based on an anchorless structure for high operating temperature (>;200°C). The proposed NEM NVM device has two stable mechanical states obtained by adhesion forces, and is actuated by electrostatic forces. This work further discusses the modeling of the NEM memory device and the scaling effects on the device performance. Finally, a memory cell consisting of the NEM memory device and two MOS transistors (1NEM-2T), and NEM NVM array structure are presented.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122725544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Analysis of the effect of boron doping on GeTe Phase Change Memories 硼掺杂对GeTe相变存储器的影响分析
2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241873
C. Sandhya, A. Bastard, L. Perniola, J. Bastien, A. Toffoli, E. Henaff, A. Roule, A. Persico, B. Hyot, V. Sousa, B. De Salvo, G. Reimbold
{"title":"Analysis of the effect of boron doping on GeTe Phase Change Memories","authors":"C. Sandhya, A. Bastard, L. Perniola, J. Bastien, A. Toffoli, E. Henaff, A. Roule, A. Persico, B. Hyot, V. Sousa, B. De Salvo, G. Reimbold","doi":"10.1109/IRPS.2012.6241873","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241873","url":null,"abstract":"For the first time, we evaluate the electrical behavior of boron doped GeTe Phase-Change Memories (PCM). Our results demonstrate 25% RESET current reduction and excellent resistance contrast between SET and RESET states with B doping. A further benefit of controlled SET dynamics makes it favorable for MLC applications. Finally, we demonstrate that boron doped GeTe phase change materials maintain good device endurance reliability.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122563745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Practical implications of chip-level statistical electromigration 芯片级统计电迁移的实际意义
2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241867
A. Schmitz
{"title":"Practical implications of chip-level statistical electromigration","authors":"A. Schmitz","doi":"10.1109/IRPS.2012.6241867","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241867","url":null,"abstract":"The accurate setting of electromigration (EM) design guidelines early is necessary to achieve chip-level fail goals. The issue is even more critical with the recognition of the percentage fail as a stochastic issue based on the individual EM elements. The challenge is the degree to fix those elements prior to the knowledge of chip-level fail rate. This paper will demonstrate a test case and approaches to early design guidelines which have shown success at meeting chip-level EM fail goals.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"311 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122805053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Design and fabrication of SiGe MEMS structures with high intrinsic ESD robustness 高ESD稳健性SiGe MEMS结构的设计与制造
2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241822
S. Sangameswaran, V. Cherman, J. de Coster, A. Witvrouw, G. Groeseneken, I. De Wolf
{"title":"Design and fabrication of SiGe MEMS structures with high intrinsic ESD robustness","authors":"S. Sangameswaran, V. Cherman, J. de Coster, A. Witvrouw, G. Groeseneken, I. De Wolf","doi":"10.1109/IRPS.2012.6241822","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241822","url":null,"abstract":"The mechanical response of electrostatically-actuated MEMS to ESD stress leads to contact breakdown or to discharges across micro-gaps. This is the root cause of most MEMS failures under ESD stress. This paper discusses improvement of the intrinsic ESD robustness of SiGe MEMS from Class0 (<;250V) to more than Class1 (>;500V), through smart design variations and higher mechanical stiffness. A MEMS-based one-time ESD-protection fuse with pre-defined trigger voltage is shown as an application.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129417287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信