Ramesh Vaddi, T. T. Kim, Vincent Pott, J. T. M. Lin
{"title":"Design and analysis of anchorless shuttle nano-electro-mechanical non-volatile memory for high temperature applications","authors":"Ramesh Vaddi, T. T. Kim, Vincent Pott, J. T. M. Lin","doi":"10.1109/IRPS.2012.6241917","DOIUrl":null,"url":null,"abstract":"This paper presents a novel nano-electro-mechanical (NEM) non-volatile memory (NVM) based on an anchorless structure for high operating temperature (>;200°C). The proposed NEM NVM device has two stable mechanical states obtained by adhesion forces, and is actuated by electrostatic forces. This work further discusses the modeling of the NEM memory device and the scaling effects on the device performance. Finally, a memory cell consisting of the NEM memory device and two MOS transistors (1NEM-2T), and NEM NVM array structure are presented.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE International Reliability Physics Symposium (IRPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRPS.2012.6241917","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper presents a novel nano-electro-mechanical (NEM) non-volatile memory (NVM) based on an anchorless structure for high operating temperature (>;200°C). The proposed NEM NVM device has two stable mechanical states obtained by adhesion forces, and is actuated by electrostatic forces. This work further discusses the modeling of the NEM memory device and the scaling effects on the device performance. Finally, a memory cell consisting of the NEM memory device and two MOS transistors (1NEM-2T), and NEM NVM array structure are presented.