Reliability characterization of 32nm high-k metal gate SOI technology with embedded DRAM

Abstract

The reliability characterization of a high performance 32nm SOI CMOS technology featuring gate first High-K Metal Gate and embedded High-K Metal Fill DRAM is presented. This technology features high performance 0.9V thin dielectric devices and 1.5V thick dielectric I/O devices. Included are results of Hot Carrier, Bias Temperature, Planar and Trench Node TDDB, Gate to Contact, silicon eFUSE, SER, SRAM and Logic circuit reliability evaluations.