Role of grain boundary percolative defects and localized trap generation on the reliability statistics of high-κ gate dielectric stacks

N. Raghavan, K. Pey, K. Shubhakar, X. Wu, W. H. Liu, M. Bosman
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引用次数: 23

Abstract

Grain boundary (GB) microstructural defects in polycrystalline high-? dielectric thin films may cause localized non-random trap generation during the percolation breakdown (BD) process. We study the effect of this non-random trap generation on the reliability statistics of the metal gate (MG) - high-κ (HK) stack. For the first time, we propose a fundamental physics-based Kinetic Monte Carlo (KMC) model considering the thermodynamics and kinetics of bond breaking, generation of oxygen vacancy traps and simulating the trap evolution process in a dual-layer HK - interfacial layer (IL) gate stack. Our simulation model helps explain the non-Weibull distribution trends for time dependent dielectric breakdown data (TDDB) and also determine the sequence of BD which is found to be independent of the thickness ratio of (tHK : tIL) and gate voltage (Vg). Results show that the IL layer is always more susceptible to early percolation and circuit level failure may only be caused by multiple soft BD (SBD) events in the IL layer. The possibility of a sequential IL → HK breakdown is very unlikely for operating voltage conditions of Vop = 1V.
晶界渗透缺陷和局域陷阱产生对高κ栅介电堆可靠性统计的影响
多晶界(GB)显微组织缺陷介电薄膜在渗透击穿过程中会产生局部非随机陷阱。我们研究了这种非随机陷阱的产生对金属栅(MG) -高-κ (HK)堆叠可靠性统计的影响。本文首次提出了一个基于基本物理的动力学蒙特卡罗(KMC)模型,该模型考虑了键断裂的热力学和动力学,氧空位陷阱的产生,并模拟了双层HK -界面层(IL)栅极堆栈中的陷阱演化过程。我们的模拟模型有助于解释随时间变化的介质击穿数据(TDDB)的非威布尔分布趋势,并确定与厚度比(tHK: tIL)和栅电压(Vg)无关的BD序列。结果表明,IL层总是更容易发生早期渗透,电路级故障可能仅由IL层中的多个软BD (SBD)事件引起。在Vop = 1V的工作电压条件下,顺序IL→HK击穿的可能性很小。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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