S. Pae, C. Prasad, S. Ramey, J. Thomas, A. Rahman, R. Lu, J. Hicks, S. Batzer, Q. Zhao, J. Hatfield, M. Liu, C. Parker, B. Woolery
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Gate dielectric TDDB characterizations of advanced High-k and metal-gate CMOS logic transistor technology
Transition into High-K (HK) dielectric and Metal-Gate (MG) in advanced logic process has enabled continued technology scaling in support of Moore's law [1-2]. With this, CMOS operating fields have been increasing along with gate dielectric TDDB voltage acceleration factors (VAF). VAF is the most critical reliability parameter used to accurately predict the Gate oxide lifetime (TDDB) at use. This paper highlights low voltage (low-V) TDDB data is critical for the accurate assessment of HK+MG VAF and provides further evidences from both transistor- and product-level data based on 32nm technology generations.