用于复杂互连几何形状的后端介电芯片可靠性模拟器

2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI:10.1109/IRPS.2012.6241878

Chang-Chih Chen, M. Bashir, L. Milor, Daehyun Kim, S. Lim

{"title":"用于复杂互连几何形状的后端介电芯片可靠性模拟器","authors":"Chang-Chih Chen, M. Bashir, L. Milor, Daehyun Kim, S. Lim","doi":"10.1109/IRPS.2012.6241878","DOIUrl":null,"url":null,"abstract":"Backend dielectric breakdown degrades the reliability of circuits. We present test data and a methodology to estimate chip lifetime due to backend dielectric breakdown. Our methodology incorporates failures due to parallel tracks, the width effect, and field enhancement due to line ends. The impact of line ends has been found to be very significant experimentally, and it is demonstrated that this component can dominate the failure rate of the chip due to dielectric breakdown.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"Backend dielectric chip reliability simulator for complex interconnect geometries\",\"authors\":\"Chang-Chih Chen, M. Bashir, L. Milor, Daehyun Kim, S. Lim\",\"doi\":\"10.1109/IRPS.2012.6241878\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Backend dielectric breakdown degrades the reliability of circuits. We present test data and a methodology to estimate chip lifetime due to backend dielectric breakdown. Our methodology incorporates failures due to parallel tracks, the width effect, and field enhancement due to line ends. The impact of line ends has been found to be very significant experimentally, and it is demonstrated that this component can dominate the failure rate of the chip due to dielectric breakdown.\",\"PeriodicalId\":341663,\"journal\":{\"name\":\"2012 IEEE International Reliability Physics Symposium (IRPS)\",\"volume\":\"101 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-04-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE International Reliability Physics Symposium (IRPS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IRPS.2012.6241878\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE International Reliability Physics Symposium (IRPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRPS.2012.6241878","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 12

摘要

后端介质击穿降低了电路的可靠性。我们提出了测试数据和方法来估计芯片寿命由于后端电介质击穿。我们的方法包含了由于平行轨迹、宽度效应和由于线端引起的场增强而导致的故障。实验发现，线路端部的影响是非常显著的，并且证明了该元件可以控制由于介质击穿而导致的芯片故障率。

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Backend dielectric chip reliability simulator for complex interconnect geometries

Backend dielectric breakdown degrades the reliability of circuits. We present test data and a methodology to estimate chip lifetime due to backend dielectric breakdown. Our methodology incorporates failures due to parallel tracks, the width effect, and field enhancement due to line ends. The impact of line ends has been found to be very significant experimentally, and it is demonstrated that this component can dominate the failure rate of the chip due to dielectric breakdown.

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2012 IEEE International Reliability Physics Symposium (IRPS)

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