27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium最新文献_第3页

A new architecture for equipment and clusters for backend processes 为后端流程的设备和集群提供了新的架构

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032787

M. Lichtveld, B. van der Zon

{"title":"A new architecture for equipment and clusters for backend processes","authors":"M. Lichtveld, B. van der Zon","doi":"10.1109/IEMT.2002.1032787","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032787","url":null,"abstract":"For years, semiconductor backend manufacturing has shown a trend for automation and integration of processes and equipment. The goals to be achieved are well known: reduction of cycle time, WIP material handling, and improvement of equipment utilization to name a few. The challenges for equipment manufacturers and integrators are maximizing functionality and flexibility, while minimizing complexity and cost. While equipment manufacturers must deal with short time-to-market and difficulties of integrating new processes in their equipment, integrators are confronted with differences in interpretation of standards by equipment manufacturers. All these problems can be tackled by a different approach to system architecture and design. This paper presents such a new approach to system architecture and design for equipment and clusters in the semiconductor backend industry. Because no fundamental differentiation is made between process integration and equipment integration, the same generic components (mechanical, electrical and software) can be used to build-equipment or clusters. Finally, this paper shows how this system architecture can be applied in the design of standalone equipment as well as in the design of clusters.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116884676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Effect of underfill fillet configuration on flip chip package reliability 下填角结构对倒装芯片封装可靠性的影响

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032769

L. Nguyen, H. Nguyen

{"title":"Effect of underfill fillet configuration on flip chip package reliability","authors":"L. Nguyen, H. Nguyen","doi":"10.1109/IEMT.2002.1032769","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032769","url":null,"abstract":"With flip chip processing, sufficient underfill material needs to be present during assembly to ensure a fillet around the die. The volume of underfill used governs the fillet shape, regardless of the application method, e.g., standard capillary deposition, no-flow, or wafer level underfill. There has been more interest with the latter method due to the paradigm shift in processing. Advantages and challenges exist with wafer level underfill. One concern is the fillet shape obtainable for a given pre-applied film thickness and flow characteristics, which are governed by the curing mechanisms. This paper presents experimental and modeling results of the effects of fillet configurations on flip chip reliability. Configurations with and without fillets were made with different underfills on flip chip dies on ceramic substrates. The packages were thermally cycled, electrically tested and scanned with acoustic microscopy to check for interfacial delamination. Finite element models were also generated for the different configurations and materials to provide relative merits on the material/configuration aspects. The results indicated that the presence of fillets is as equally important as the selection of the underfill material for the best thermal cycling performance. Thus, ensuring that the proper coating thickness is obtained will be critical to good die filleting and package reliability in wafer level underfill processing.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114373698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Achieving a world record in ultra high speed wire bonding through novel technology 通过新技术实现超高速线键合的世界纪录

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032776

M. Barp, D. Vischer

{"title":"Achieving a world record in ultra high speed wire bonding through novel technology","authors":"M. Barp, D. Vischer","doi":"10.1109/IEMT.2002.1032776","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032776","url":null,"abstract":"The traditional wire bonder design employs a pivoting z-axis, which is mounted on an orthogonal x/y-stage. This type of system is now approaching its physical limitations. The new revolutionary and unique bond head design described in this paper uses entirely new kinematics, which allows for higher accelerations, as well as a stiff, light design. The vibrations, even at highest speed, can be reduced to a level that is not conceivable with conventional designs. These equipment capabilities can be used to redefine process-related issues, such as looping, and ball and wedge formation, where low vibrations at high speed are crucial. This new technology achieved a world record in high-speed wire bonding in the lab and leads to a UPH increase of more than 60% with respect to today's conventional best class designs. The benefit of this revolutionary design for the back end manufacturer is the prolonged life expectancy of wire bonding, as the standard interconnect technology. Manufacturers will continue to realize cost savings through productivity improvements and reduce their risk by remaining with a standard that has flourished for decades.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"308 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114711448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

Reliability issues in direct chip attach assemblies using reflow or no-flow underfill 使用回流或无流底填料的直接芯片连接组件的可靠性问题

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032726

V. Patwardhan, D. Blass, P. Borgesen, K. Srihari

{"title":"Reliability issues in direct chip attach assemblies using reflow or no-flow underfill","authors":"V. Patwardhan, D. Blass, P. Borgesen, K. Srihari","doi":"10.1109/IEMT.2002.1032726","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032726","url":null,"abstract":"The encapsulation or underfilling of flip chips is critical for the widespread success of flip-chip-on-board type assemblies. The use of an underfill reduces the stresses on the solder joints that result from the coefficient of thermal expansion (CTE) mismatch between the different materials. The mismatch in the CTE between the chip, solder joint, and the substrate influences the reliability of the assembly. This mismatch results in cracks being initiated at the high stress points which eventually leads to failure of the flip chip assembly. In addition to increased performance and reliability that is achieved by the use of underfill, it is also necessary to have enhanced characteristics for faster, in-line processing of these materials. Reflow or no-flow encapsulants allow the underfill process to be a part of the surface mount process sequence, and do not require an off-line encapsulant dispense step. The use of these materials leads to other reliability concerns including delamination of the encapsulant material from the passivation interface, encapsulant fillet cracking, solder extrusions and bridging through fissures in the encapsulant, moisture ingress into substrates and issues due to mask mis-registration. This paper reports on experimental work that evaluated reflow or no-flow underfill materials. Some of the parameters varied for the evaluation include encapsulant dispense pattern, passivation type, die pitch, and bump layout.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126427134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Experimental and computational modelling characterisation of fine particle Pb-free solder paste volumes for flip chip assembly applications 用于倒装芯片组装应用的细颗粒无铅锡膏体积的实验和计算模型表征

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032770

G. Jackson, M. Hendriksen, Hua Lu, Nduka Nnamdi (Ndy) Ekere

{"title":"Experimental and computational modelling characterisation of fine particle Pb-free solder paste volumes for flip chip assembly applications","authors":"G. Jackson, M. Hendriksen, Hua Lu, Nduka Nnamdi (Ndy) Ekere","doi":"10.1109/IEMT.2002.1032770","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032770","url":null,"abstract":"Advanced flip-chip technology is the key technique used to achieve a high-density assembly of components onto printed circuit boards (PCB). Increasing demands are being made on electronics manufacturers to use flip chip components with greater input/output capabilities at pitches below 0.100 mm for their future applications. Furthermore, the advancement in this technology is challenged by the requirement to use new Pb-free materials for interconnections; this being driven by the European directive, Waste from Electronic and Electrical Equipment (WEEE) that necessitates the elimination of lead containing materials from electronics products by January 2006. The advancements in flip chip technology place a requirement for ultra small solder volumes in joint interconnection. Volume also plays a significant role towards the long-term reliability of the joints. Computational modelling can yield reliability data and required solder volumes for flip chip interconnection. However, in order to implement small solder volumes into a flip chip assembly process, a firm understanding of the formation and subsequent behaviour throughout the process is required. In this investigation, stencil printing of Pb-free solder paste via small stencil apertures, required for ultra fine pitch flip-chip applications, is reported, highlighting the issues encountered at such small geometries.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121710866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Overcoming the key barriers in 35 /spl mu/m pitch wire bond packaging: probe, mold, and substrate solutions and trade-offs 克服35 /spl亩/米间距线键合封装的关键障碍:探头、模具和基板解决方案和权衡

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032747

B. Chylak, S. Tang, L. Smith, F. Keller

引用次数: 2

Measurement challenges for on-wafer RF-SOC test 圆片上RF-SOC测试的测量挑战

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032778

Wai Lau

{"title":"Measurement challenges for on-wafer RF-SOC test","authors":"Wai Lau","doi":"10.1109/IEMT.2002.1032778","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032778","url":null,"abstract":"With the wireless industry pushing towards higher levels of integration, with more system-in-a-package (SIP) and multi-chip module (MCM) technology, known-good-die testing of RF-SOC devices has emerged as the next test challenge. These devices have higher packaging costs compared to the traditional single die integrated circuits (ICs), and potential lower yields, since multiple dice are used. As a result, the cost to perform comprehensive on-wafer testing is outweighed by the cost to scrap the devices during the final package test. In addition, some IC manufacturers are selling bare die to be used in the SIP or MCM of another manufacturer. On-wafer test is then required to ensure that good product is shipped. This paper will use a Bluetooth radio modem chip as an example to discuss the measurement challenges and considerations for known-good die testing of a RF-SOC device. With this example, the difficulty of testing RF functionality on-wafer will be compounded by the need to source and measure RF and digital signals simultaneously, creating signal integrity issues. This paper will explore the challenges of laying out the printed circuit board for the device under test (DUT), including setup of the wafer probe card and assembly. Factors taken into account when selecting a probe station, RF wafer probe card, and ATE test system will then be discussed. This paper will conclude with a discussion of on-wafer calibration, including challenges and solutions. Real results from the Bluetooth radio modem chip example will be used to further the discussion.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124645933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

A novel process for protecting wire bonds from sweep during molding 一种保护线键在成型过程中不受波及的新工艺

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032775

A. Hmiel, R. Wicen, S. Tang

{"title":"A novel process for protecting wire bonds from sweep during molding","authors":"A. Hmiel, R. Wicen, S. Tang","doi":"10.1109/IEMT.2002.1032775","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032775","url":null,"abstract":"Wire bonding remains the lowest cost and most flexible method for interconnection of semiconductors. A major factor limiting the density of this widely used interconnect technology is wire sweep during the molding processes. Design rules for wire length, wire diameter and bond pad pitch are in many cases constrained by the need to avoid sweep, potentially compromising manufacturers' ability to keep pace with industry roadmaps. For gold wire diameters of 25-30 /spl mu/m, the wire stiffness allows the molding process some latitude. As wire diameters shrink to fit the ball bonds on the periphery of smaller or more complex devices, the molding process has difficulty avoiding wire sweep. The wire encapsulation process described in this paper reduces sweep by as much as an order of magnitude for conventional as well as alternative designs, such as 3D packaging. This paper presents a process that protects the wires in such a way that wire sweep is not a constraint so that assemblers can continue to extend the capabilities of wire bonding. Two process methods are discussed, a batch method and an integrated wirebonder dispense and cure method. The reliability performance of packages made using these processes has been assessed and is reported. The encapsulated test vehicles have achieved JEDEC 3 preconditioning with 3/spl times/ reflow at 240/spl deg/C, temperature cycling and other accelerated life cycle reliability tests. Success at passing JEDEC level 3 and 260/spl deg/ has also been achieved.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128883818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Adhesion and reliability of underfill/subtrate interfaces in flip chip BGA packages: metrology and characterization 倒装BGA封装中底填/衬底接口的附着力和可靠性:计量和表征

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032755

K. Nagarajan, R. Dauskardt

引用次数: 11

Bringing test to design: testing in the designer's event based environment 将测试带入设计:在设计师基于事件的环境中进行测试

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032781

R. Rajsuman

引用次数: 3