27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium最新文献

High reliability non-flow underfill material with filler loading 高可靠性不流动底填料材料，填料加载

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032728

S. Katsurayama, Y. Sakamoto

引用次数: 4

Gold stud bump in flip-chip applications 倒装芯片应用中的金螺柱凸点

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032735

J. Jordan

引用次数: 33

Encapsulation of 1-Up fpBGA from design to production 1-Up fpBGA从设计到生产的封装

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032748

H. Sze, R. Tsang, Y. Jaramillo

{"title":"Encapsulation of 1-Up fpBGA from design to production","authors":"H. Sze, R. Tsang, Y. Jaramillo","doi":"10.1109/IEMT.2002.1032748","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032748","url":null,"abstract":"The plastic near chip scale ball grid array (fpBGA) package has already begun to take over certain segments of the surface mount technology (SMT) industry, and its hold on the market is expected to continue growing over the next few years. A fpBGA in general, offers a smaller footprint than a QFP package with similar pin count. In addition, fpBGA significantly reduces the risk of component handling damage, reduces power supply noise and offers the same or better performance than leaded packages. With the ever-increasing demand for high density, high I/O count packaging, fpBGA is fast becoming the next generation package. fpBGA package is a method of reducing package size and its pin-to-pin trace gap in order to integrate more functions and reliability in a single space. Conventional encapsulation methodology for fpBGA is by panel molding, normally into multiple (4 or 5) sections. This reduces the substrate material utilization. In this paper design methodology and package reliability for a 1-up (I section) fpBGA will be presented. Reliability consideration includes JEDEC package reliability standard. Package reliability data will be discussed. Package co-planarity data will be compared. The encapsulation results to be discussed will include EMC selection criteria, PMC techniques to control warpage, and the cause of kinked wire and its control methodology.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127208911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Managing test complexity through a comprehensive design-to-test strategy 通过全面的设计到测试策略来管理测试复杂性

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032779

M. Kondrat

{"title":"Managing test complexity through a comprehensive design-to-test strategy","authors":"M. Kondrat","doi":"10.1109/IEMT.2002.1032779","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032779","url":null,"abstract":"Advances in design capabilities and process technologies enable semiconductor manufacturers to create increasingly sophisticated, high-speed integrated circuits with test requirements that seriously challenge traditional test methods and manufacturers' ability to achieve high volume, cost-effective production. To cope with increased test complexity, alternative approaches have largely focused in isolation on design-centric or production-centric tactics, relying in some cases on design-for-test (DFT) methods and in other cases on more powerful automatic test equipment (ATE). Yet approaches to test based solely on such tactics have already fallen behind advances in design and manufacturing, exposing IC manufacturers to the real possibility of creating advanced ICs that cannot be tested within reasonable limits of time or cost. In contrast, a more effective approach targets growing test complexity through a broader strategy that spans product development to facilitate the critical transition from design to production test. At the heart of this strategic approach, test development tools operate within existing design flows, smoothing the traditional barriers between design and test. As a result, logic designers are able to build more testable ICs, and test engineers are able to write more effective test programs. This paper discusses the challenges limiting traditional test methods; describes the requirements for more effective solutions based on a comprehensive design-to-test strategy; and discusses critical technologies needed to deploy effective design-to-test methods required to manage emerging test requirements.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123665971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Laser processing - the future of HDI manufacturing 激光加工——HDI制造业的未来

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032742

S. Venkat, T. Hannon

{"title":"Laser processing - the future of HDI manufacturing","authors":"S. Venkat, T. Hannon","doi":"10.1109/IEMT.2002.1032742","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032742","url":null,"abstract":"Conventional electronics manufacturing technologies have become unsuitable for high density interconnect structures (HDIS) due to processing limitations, lower manufacturing yields, higher production costs and limited flexibility. Laser processing is one suitable solution for manufacturing HDIS. This is supported by published reports that over 90% of all microvias in HDI PWBs and chip package substrates are formed using laser technology (D.F. Downey et al, 1993). Lasers are ideal primarily due to their high-resolution processing capabilities, fast processing speeds, reliability, versatility and lower cost-of-ownership. Focusing on these factors, this paper highlights key developments in laser processing which are relevant for advancing HDI technology. Particular emphasis is placed on new developments in CO/sub 2/, UV and diode-pumped solid-state laser processing for improved HDI fabrication. Laser performance characteristics, including optimal selection of key process parameters for improved HDI fabrication, and cost-of-ownership models are presented for each laser technology. After discussing the benefits of using existing laser technologies for HDI manufacturing, this paper provides an insight into emerging laser technologies, which are currently under development and driven by the electronics industry. A preview of these technologies and the potential capabilities for the electronics manufacturing industry are presented.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122551654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Reliability testing of single diffused planar InP/InGaAs avalanche photodiodes 单扩散平面InP/InGaAs雪崩光电二极管可靠性测试

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032752

Jihoun Jung, Yong-Hwan Kwon, K. Hyun, I. Yun

引用次数: 1

High density photolithographic Advanprobe/spl trade/ technology 高密度光刻探针/spl贸易/技术

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032791

D. Yu, Yu Zhou, B. Aldaz, K. Lee

引用次数: 0

Elimination of polyimide stress buffer on integrated circuits using advanced packaging materials 消除聚酰亚胺应力缓冲集成电路使用先进的封装材料

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032753

D. Patten, Jesse Phou

{"title":"Elimination of polyimide stress buffer on integrated circuits using advanced packaging materials","authors":"D. Patten, Jesse Phou","doi":"10.1109/IEMT.2002.1032753","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032753","url":null,"abstract":"Polyimide is typically used as the final layer in silicon technology process integration. Its primary purpose is to protect the topside structures and relieve the interface of stresses introduced during and after encapsulation. However, developments in mold compound technology as well as in wafer fabrication techniques have caused the industry to re-evaluate the need for a polyimide stress buffer. Mold compound fillers have become finer and more spherical, reducing particulate pressure loading from the fillers on the die top surface. Additionally, the use of CMP in wafer fabrication reduces topographical variations, which result in less stress points on the die surface., This paper presents the evaluations that were conducted to assess the continued use of polyimide, and the effort made to eliminate if from some microelectronic packages. Moisture characterization data for several MAPBGA packages are included and package performance without polyimide is assessed. It was concluded that the removal of polyimide from these devices does not significantly affect the yields, but more work needs to be done to realize the limitations.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130764931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Novel techniques for wideband RF test 宽带射频测试新技术

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032793

J. Lukez

引用次数: 14

Processing strategies for high speed 0201 implementation 高速0201实现的处理策略

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032745

P. Houston, J. Bentley, B. Lewis, B.A. Smith, D. Baldwin

{"title":"Processing strategies for high speed 0201 implementation","authors":"P. Houston, J. Bentley, B. Lewis, B.A. Smith, D. Baldwin","doi":"10.1109/IEMT.2002.1032745","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032745","url":null,"abstract":"A lot of research has been done to determine the board design considerations for 0201 processing, but work also needs to be done to determine the process window. Initial data presented last year showed a number of significant factors in the printing, placement, and reflow processes. From that study, the individual process steps showed that certain design and manufacturing parameters can have a huge effect upon total process defects. Presented in this paper is the data from those studies as well as the data gathered after a large evaluation run in which many components were processed. Studied process parameters were broken out by individual process steps initially, and then studied over the entire process. Some of the process parameters that were examined were stencil manufacturing method, print force, print speed, and stencil wipe frequency for the printing process and reflow atmosphere, profile shape, and ramp rate for the reflow process. From these studies, a reliable process window was obtained for a high speed 0201 assembly process that was proven to provide a 17 DPM (defect per million) assembly yield.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133211184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5