将测试带入设计:在设计师基于事件的环境中进行测试

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI:10.1109/IEMT.2002.1032781

R. Rajsuman

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引用次数: 3

摘要

本文提出了一种可以在集成电路设计者的仿真环境中工作的新型测试器，取代了传统的ATE测试环境。该测试仪使用来自vcd格式的Verilog或VHDL模拟器的IC仿真数据。介绍了测试仪的基本结构和工作原理。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Bringing test to design: testing in the designer's event based environment

In this paper, we present a new tester that works in the IC designer's simulation environment instead of traditional ATE test environment. The tester uses IC simulation data from a Verilog or VHDL simulator in the vcd format. The basic tester architecture and its operation are described.

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来源期刊

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium

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