用于倒装芯片组装应用的细颗粒无铅锡膏体积的实验和计算模型表征

G. Jackson, M. Hendriksen, Hua Lu, Nduka Nnamdi (Ndy) Ekere
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引用次数: 0

摘要

先进的倒装芯片技术是实现元件在印刷电路板(PCB)上高密度组装的关键技术。对于电子制造商来说,越来越多的需求是在未来的应用中使用具有更大输入/输出能力的倒装芯片组件,其间距小于0.100 mm。此外,该技术的进步受到要求使用新的无铅材料进行互连的挑战;这是由欧洲指令推动的,电子和电气设备废物(WEEE)要求在2006年1月之前消除电子产品中的含铅材料。倒装芯片技术的进步对接头互连的焊料体积提出了要求。体积对关节的长期可靠性也起着重要的作用。计算模型可以产生可靠性数据和倒装芯片互连所需的焊料量。然而,为了在倒装芯片组装过程中实现小体积的焊料,需要对整个过程的形成和后续行为有一个坚定的理解。在这项研究中,通过小孔径的模板印刷无铅锡膏,需要超细间距倒装芯片的应用,报告,突出了在这种小几何形状遇到的问题。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Experimental and computational modelling characterisation of fine particle Pb-free solder paste volumes for flip chip assembly applications
Advanced flip-chip technology is the key technique used to achieve a high-density assembly of components onto printed circuit boards (PCB). Increasing demands are being made on electronics manufacturers to use flip chip components with greater input/output capabilities at pitches below 0.100 mm for their future applications. Furthermore, the advancement in this technology is challenged by the requirement to use new Pb-free materials for interconnections; this being driven by the European directive, Waste from Electronic and Electrical Equipment (WEEE) that necessitates the elimination of lead containing materials from electronics products by January 2006. The advancements in flip chip technology place a requirement for ultra small solder volumes in joint interconnection. Volume also plays a significant role towards the long-term reliability of the joints. Computational modelling can yield reliability data and required solder volumes for flip chip interconnection. However, in order to implement small solder volumes into a flip chip assembly process, a firm understanding of the formation and subsequent behaviour throughout the process is required. In this investigation, stencil printing of Pb-free solder paste via small stencil apertures, required for ultra fine pitch flip-chip applications, is reported, highlighting the issues encountered at such small geometries.
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