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2003 IEEE International Conference on SOI最新文献

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Optimizing the salicide thickness for improving 130 nm PD SOI performances 优化水杨酸盐厚度，提高130 nm PD SOI性能
2003 IEEE International Conference on SOI Pub Date : 2003-11-03 DOI: 10.1109/SOI.2003.1242903
S. Haendler, R. Gwoziecki, C. Tabone, H. Brut, C. Raynaud
{"title":"Optimizing the salicide thickness for improving 130 nm PD SOI performances","authors":"S. Haendler, R. Gwoziecki, C. Tabone, H. Brut, C. Raynaud","doi":"10.1109/SOI.2003.1242903","DOIUrl":"https://doi.org/10.1109/SOI.2003.1242903","url":null,"abstract":"The impact of an increased cobalt salicide thickness on MOS circuit performances for 130 nm node PD-SOI is analyzed. By adjusting the cobalt deposition thickness, low gate resistance, as well as better control of I/sub OFF/ for NMOS are achieved. Using devices and \"circuits\" results, it is shown that static current consumption is decreased by a factor 10 without compromising the dynamic performances, whereas the gate resistance is reduced by a factor 2-3 and the static noise margin for SRAM is improved by 10%.","PeriodicalId":329294,"journal":{"name":"2003 IEEE International Conference on SOI","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121117144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Corner effect in multiple-gate SOI MOSFETs 多栅极SOI mosfet中的拐角效应
2003 IEEE International Conference on SOI Pub Date : 2003-11-03 DOI: 10.1109/SOI.2003.1242919
W. Xiong, J. W. Park, J. Colinge
{"title":"Corner effect in multiple-gate SOI MOSFETs","authors":"W. Xiong, J. W. Park, J. Colinge","doi":"10.1109/SOI.2003.1242919","DOIUrl":"https://doi.org/10.1109/SOI.2003.1242919","url":null,"abstract":"Separate formation of channels in corners and sides of triple-gate SOI MOSFETs is observed. This phenomenon degrades the I/sub on//I/sub off/ ratio and the subthreshold slope, but it is present only if high doping concentrations and corners with a small radius of curvature are used.","PeriodicalId":329294,"journal":{"name":"2003 IEEE International Conference on SOI","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124885287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
Potential of SOI intrinsic MOSFETs for ring VCO design 环形压控振荡器设计中SOI本征mosfet的电势
2003 IEEE International Conference on SOI Pub Date : 2003-11-03 DOI: 10.1109/SOI.2003.1242880
D. Levacq, L. Vancaillie, D. Flandre
{"title":"Potential of SOI intrinsic MOSFETs for ring VCO design","authors":"D. Levacq, L. Vancaillie, D. Flandre","doi":"10.1109/SOI.2003.1242880","DOIUrl":"https://doi.org/10.1109/SOI.2003.1242880","url":null,"abstract":"In this paper, we study the potential of SOI MOSFETs with non-doped (or intrinsic) channels. We demonstrate that their low threshold voltage (V/sub t/) and enhanced mobility lead to power consumption reduction. Moreover, they present significantly improved linearity.","PeriodicalId":329294,"journal":{"name":"2003 IEEE International Conference on SOI","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122729516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Stand-by current in PD-SOI pseudo-nMOS circuits PD-SOI伪nmos电路的待机电流
2003 IEEE International Conference on SOI Pub Date : 2003-11-03 DOI: 10.1109/SOI.2003.1242912
J. Sivagnaname, R. B. Brown
{"title":"Stand-by current in PD-SOI pseudo-nMOS circuits","authors":"J. Sivagnaname, R. B. Brown","doi":"10.1109/SOI.2003.1242912","DOIUrl":"https://doi.org/10.1109/SOI.2003.1242912","url":null,"abstract":"In this paper, we compare the stand-by leakage power of controlled-load pseudo-nMOS circuits to that of conventional CMOS and MTCMOS in a 0.13/spl mu/m dual V/sub T/partially-depleted SOI tehnology.","PeriodicalId":329294,"journal":{"name":"2003 IEEE International Conference on SOI","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122192069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Nano-uniformity control in Unibond/sup /spl reg// process Unibond/sup /spl工艺的纳米均匀性控制
2003 IEEE International Conference on SOI Pub Date : 2003-11-03 DOI: 10.1109/SOI.2003.1242929
C. Maleville, E. Neyret, N. B. Mohamed, C. Maunand-Tussot, D. Delprat
{"title":"Nano-uniformity control in Unibond/sup /spl reg// process","authors":"C. Maleville, E. Neyret, N. B. Mohamed, C. Maunand-Tussot, D. Delprat","doi":"10.1109/SOI.2003.1242929","DOIUrl":"https://doi.org/10.1109/SOI.2003.1242929","url":null,"abstract":"This paper deals with uniformity control in Unibond process, monitored from wafer scale down to device level scale, with a discussion of metrology solutions that are utilized.","PeriodicalId":329294,"journal":{"name":"2003 IEEE International Conference on SOI","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128960441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Control of threshold voltage and short channel effects in ultra-thin strained-SOI CMOS 超薄应变型soi CMOS中阈值电压和短通道效应的控制
2003 IEEE International Conference on SOI Pub Date : 2003-11-03 DOI: 10.1109/SOI.2003.1242922
T. Numata, T. Mizuno, T. Tezuka, J. Koga, S. Takagi
{"title":"Control of threshold voltage and short channel effects in ultra-thin strained-SOI CMOS","authors":"T. Numata, T. Mizuno, T. Tezuka, J. Koga, S. Takagi","doi":"10.1109/SOI.2003.1242922","DOIUrl":"https://doi.org/10.1109/SOI.2003.1242922","url":null,"abstract":"In this paper threshold voltage, subthreshold slope and short channel effects, in strained-SOI n-MOSFET and p-MOSFET are examined quantitatively, with emphasis on the impact of band offset in Si/SiGe heterostructure, by two dimensional device simulation.","PeriodicalId":329294,"journal":{"name":"2003 IEEE International Conference on SOI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129465361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Systematic study of the splitting kinetic of H/He co-implanted substrate H/He共注入底物裂解动力学的系统研究
2003 IEEE International Conference on SOI Pub Date : 2003-11-03 DOI: 10.1109/SOI.2003.1242926
P. Nguyen, I. Cayrefourcq, B. Blondeau, N. Sousbie, C. Lagahe-Blanchard, S. Sartori, A. Cartier
{"title":"Systematic study of the splitting kinetic of H/He co-implanted substrate","authors":"P. Nguyen, I. Cayrefourcq, B. Blondeau, N. Sousbie, C. Lagahe-Blanchard, S. Sartori, A. Cartier","doi":"10.1109/SOI.2003.1242926","DOIUrl":"https://doi.org/10.1109/SOI.2003.1242926","url":null,"abstract":"In this paper, we proposed the results of a systematic study of coimplantation of hydrogen and helium. Systematic SIMS and TEM analysis have been done.","PeriodicalId":329294,"journal":{"name":"2003 IEEE International Conference on SOI","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123646003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Ultralow-voltage MTCMOS/SOI circuits for batteryless wireless system 无电池无线系统的超低电压MTCMOS/SOI电路
2003 IEEE International Conference on SOI Pub Date : 2003-11-03 DOI: 10.1109/SOI.2003.1242877
T. Douseki, H. Kyuragi
{"title":"Ultralow-voltage MTCMOS/SOI circuits for batteryless wireless system","authors":"T. Douseki, H. Kyuragi","doi":"10.1109/SOI.2003.1242877","DOIUrl":"https://doi.org/10.1109/SOI.2003.1242877","url":null,"abstract":"Ultralow-power multi-threshold (MT) CMOS/SOI circuit technology, which makes it possible to lower the supply voltage of LSIs to 0.5 V and reduce power dissipation to the 1-mW level, provides self-powered batteryless operation for short-range wireless system. We overview MTCMOS/SOI circuit technology and describe some batteryless wireless systems built using MTCMOS/SOI LSIs.","PeriodicalId":329294,"journal":{"name":"2003 IEEE International Conference on SOI","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121339333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Peculiarities of the temperature behavior of SOI MOSFETs in the deep submicron area SOI mosfet在深亚微米区域温度行为的特性
2003 IEEE International Conference on SOI Pub Date : 2003-11-03 DOI: 10.1109/SOI.2003.1242906
L. Vancaillie, V. Kilchytska, P. Delatte, L. Demeus, H. Matsuhashi, F. Ichikawa, D. Flandre
{"title":"Peculiarities of the temperature behavior of SOI MOSFETs in the deep submicron area","authors":"L. Vancaillie, V. Kilchytska, P. Delatte, L. Demeus, H. Matsuhashi, F. Ichikawa, D. Flandre","doi":"10.1109/SOI.2003.1242906","DOIUrl":"https://doi.org/10.1109/SOI.2003.1242906","url":null,"abstract":"In this paper, the temperature dependence of transistor fabricated in a thin film deep submicron SOI MOSFET fully depleted process, junction leakage current and transconductance were evaluated.","PeriodicalId":329294,"journal":{"name":"2003 IEEE International Conference on SOI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130479059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Surface smoothing effect in patterned SOI fabrication with SIMOX technology SIMOX工艺制做图案化SOI的表面平滑效应
2003 IEEE International Conference on SOI Pub Date : 2003-11-03 DOI: 10.1109/SOI.2003.1242892
T. Sasaki, S. Takayama, K. Kawamura, T. Maeda, Y. Nagatake, A. Matsumura
{"title":"Surface smoothing effect in patterned SOI fabrication with SIMOX technology","authors":"T. Sasaki, S. Takayama, K. Kawamura, T. Maeda, Y. Nagatake, A. Matsumura","doi":"10.1109/SOI.2003.1242892","DOIUrl":"https://doi.org/10.1109/SOI.2003.1242892","url":null,"abstract":"Patterned SOI wafers are successfully fabricated with low dose-internal thermal oxidation-SIMOX (LD-ITOX-SIMOX) process. Surfaces of SOI and bulk regions are shown to be almost at the same height level regardless of large volume expansion at buried oxide (BOX) in SOI region because of surface smoothing effect of ITOX-SIMOX anneal.","PeriodicalId":329294,"journal":{"name":"2003 IEEE International Conference on SOI","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134394669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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