S. Haendler, R. Gwoziecki, C. Tabone, H. Brut, C. Raynaud
{"title":"优化水杨酸盐厚度,提高130 nm PD SOI性能","authors":"S. Haendler, R. Gwoziecki, C. Tabone, H. Brut, C. Raynaud","doi":"10.1109/SOI.2003.1242903","DOIUrl":null,"url":null,"abstract":"The impact of an increased cobalt salicide thickness on MOS circuit performances for 130 nm node PD-SOI is analyzed. By adjusting the cobalt deposition thickness, low gate resistance, as well as better control of I/sub OFF/ for NMOS are achieved. Using devices and \"circuits\" results, it is shown that static current consumption is decreased by a factor 10 without compromising the dynamic performances, whereas the gate resistance is reduced by a factor 2-3 and the static noise margin for SRAM is improved by 10%.","PeriodicalId":329294,"journal":{"name":"2003 IEEE International Conference on SOI","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Optimizing the salicide thickness for improving 130 nm PD SOI performances\",\"authors\":\"S. Haendler, R. Gwoziecki, C. Tabone, H. Brut, C. Raynaud\",\"doi\":\"10.1109/SOI.2003.1242903\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The impact of an increased cobalt salicide thickness on MOS circuit performances for 130 nm node PD-SOI is analyzed. By adjusting the cobalt deposition thickness, low gate resistance, as well as better control of I/sub OFF/ for NMOS are achieved. Using devices and \\\"circuits\\\" results, it is shown that static current consumption is decreased by a factor 10 without compromising the dynamic performances, whereas the gate resistance is reduced by a factor 2-3 and the static noise margin for SRAM is improved by 10%.\",\"PeriodicalId\":329294,\"journal\":{\"name\":\"2003 IEEE International Conference on SOI\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-11-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2003 IEEE International Conference on SOI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOI.2003.1242903\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2003 IEEE International Conference on SOI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.2003.1242903","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Optimizing the salicide thickness for improving 130 nm PD SOI performances
The impact of an increased cobalt salicide thickness on MOS circuit performances for 130 nm node PD-SOI is analyzed. By adjusting the cobalt deposition thickness, low gate resistance, as well as better control of I/sub OFF/ for NMOS are achieved. Using devices and "circuits" results, it is shown that static current consumption is decreased by a factor 10 without compromising the dynamic performances, whereas the gate resistance is reduced by a factor 2-3 and the static noise margin for SRAM is improved by 10%.