S. Tsujikawa, K. Shiga, H. Umeda, Y. Akamatsu, J. Yugami, Y. Ohno, M. Yoneda
{"title":"V/sub ox//E/sub ox/-driven breakdown of ultra-thin SiON gate dielectric in p+gate-pMOSFET under low stress voltage of inversion mode","authors":"S. Tsujikawa, K. Shiga, H. Umeda, Y. Akamatsu, J. Yugami, Y. Ohno, M. Yoneda","doi":"10.1109/RELPHY.2005.1493114","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493114","url":null,"abstract":"We have studied the breakdown mechanism of ultra-thin SiON gate dielectrics in p+gate-pMOSFETs. A systematic study with varying gate doping concentrations has revealed that, in the case of p+gate-pMOSFETs in inversion mode, gate dielectric breakdown under low stress voltage is driven by oxide voltage (V/sub ox/) or oxide field (E/sub ox/), while the breakdown under higher stress voltage is driven by gate voltage (V/sub g/). The V/sub ox//E/sub ox/-driven breakdown which emerges under low stress voltage is quite important to the reliability of low-voltage CMOS. By studying the mechanism of the breakdown, it has been clarified that the breakdown is not induced by electron current. The concept that the breakdown is due to the same mechanism as NBTI, namely the interfacial hydrogen release driven by E/sub ox/, has been shown to be possible. However, direct tunneling of holes driven by V/sub ox/ has also been found to be a possible driving force of the breakdown. Although a decisive conclusion concerning the mechanism issue has not yet been obtained, the key factor that governs the breakdown has been shown to be V/sub ox/ or E/sub ox/.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116776052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Physical mechanism of high resistance of tungsten plug as a root cause of low yield and reliability issue in deep-sub-micron Si technology","authors":"W. Zhang, K. T. Tan","doi":"10.1109/RELPHY.2005.1493172","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493172","url":null,"abstract":"In current ULSI devices, interconnects serve an important role in enabling multilayer design and fabrication. Tungsten (W) plug processing is a common solution. The W plug resistance is critical to maintain circuit performance and reliability. Abnormal resistance can cause voltage drop and capacitance increase, which, in turn, results in longer signal propagation delay that leads to an undesirable outcome. It becomes worse with increasing interconnection complexity and operating frequency. The high via resistance failure mechanism was investigated and the impact of via etching and post-etch treatment processes were analyzed. Experimental results suggest that via etching introduces a fluorine-containing polymer residue at the via bottom. Both the polymer residue and its reaction product, AlF/sub 3/, could result in a high resistance connection. The subsequent post-etch cleaning is quite critical to assure low resistance interconnections. By optimizing the etching condition and adding lamp de-gas and vacuum bake, the accumulation of F at the via bottom was reduced and via performance was improved.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"67 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120942732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A new model for the post-breakdown conductance of MOS devices based on the generalized diode equation","authors":"E. Miranda","doi":"10.1109/RELPHY.2005.1493161","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493161","url":null,"abstract":"A new analytic model for the post-breakdown conductance of MOS devices with sub-5 nm gate oxides is presented. The model arises from the solution of the generalized diode equation, namely a diode-type equation with series resistance. The expression for the conductance-voltage characteristic is found by invoking the mathematical properties of the Lambert W function. We show that this new approach improves over a previous one, the quantum point contact model, especially in the low biases range where the contact effect between electrodes seems to play a crucial role.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127175694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Park, M.S. Rahman, M. Chang, B. Lee, M. Gardner, C. Young, H. Hwang
{"title":"Effect of high pressure deuterium annealing on electrical and reliability characteristics of MOSFETs with high-k gate dielectric","authors":"H. Park, M.S. Rahman, M. Chang, B. Lee, M. Gardner, C. Young, H. Hwang","doi":"10.1109/RELPHY.2005.1493185","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493185","url":null,"abstract":"To completely passivate the interface states of high-k gate dielectrics, we have developed a new high-pressure (up to 100 atm), pure (100%) hydrogen annealing system. Compared with the control (1 atm) forming gas (H/sub 2//Ar=4%/96%) annealed sample, high pressure (5-20 atm), pure H/sub 2/ annealing of nMOSFETs at 400/spl deg/C shows 10-15% improvement in linear drain current (I/sub d/) and maximum transconductance (g/sub m,max/). Compared with hydrogen annealing, D/sub 2/ annealed samples exhibit longer hot carrier lifetime. By optimizing the process parameters, we are able to improve both device performance and reliability characteristics.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124830057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. M. Tanner, J. Walraven, M. Dugger, T. B. Parson, S. A. Candelaria, M. Jenkins, A. Corwin, J. A. Ohlhausen, E. M. Huffman
{"title":"Accelerating aging failures in MEMS devices","authors":"D. M. Tanner, J. Walraven, M. Dugger, T. B. Parson, S. A. Candelaria, M. Jenkins, A. Corwin, J. A. Ohlhausen, E. M. Huffman","doi":"10.1109/RELPHY.2005.1493105","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493105","url":null,"abstract":"The feasibility of using temperature and humidity to age vapor-deposited SAM-coated electrostatic-actuated MEMS devices with contacting surfaces was determined. Failures were dependent on both temperature and humidity. The trend indicated longer life at both lower temperatures and lower humidity levels. Using cantilever beams, measurements reveal degradation of the VSAM (vapor-deposited self assembled monolayer) surface coating when stressed at 300/spl deg/C with controlled humidity environments of 500 and 2000 ppmv. In particular, we have seen the surface adhesion change for these beams stressed at 300/spl deg/C for time intervals of 10, 24, 50, 100, and 200 hours. However, there is no measurable change after 2 hours. The higher humidity case promotes the same surface adhesion change in a factor of ten less time. The complex MEMS devices tested followed the same trends as the beam test structures. We definitely observe a failure of the MEMS devices due to the environment with most failures occurring at 300/spl deg/C and some failures at 200/spl deg/C. These failures are due to an adhesion site in the hub of the load gear where the typical gap is 0.3 /spl mu/m.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122968630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Industry study on issues of MEMS reliability and accelerated lifetime testing","authors":"C. Fung","doi":"10.1109/RELPHY.2005.1493104","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493104","url":null,"abstract":"The paper presents the results of an industry study on issues of reliability and accelerated life testing (ALT) for micro-electro-mechanical system (MEMS) devices. The study was conducted by the MEMS Industry Group (MIG) through surveying MEMS companies and holding working group meetings in MIG sponsored conferences participated by membership companies. The survey first established the type of MEMS companies and the categories of devices involved. It then focused on the expectation, perception and state of the respondent's product lifetime, reliability issues, failure investigation and accelerated life testing. Finally, the needs of the survey participators were addressed.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114189616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reliability investigations for manufacturable high density PRAM","authors":"K. Kim, S. Ahn","doi":"10.1109/RELPHY.2005.1493077","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493077","url":null,"abstract":"In this paper, PRAM (phase-change memory), exploiting new memory materials called chalcogenides, is introduced. The reliability issues for high-density commercial memory products such as disturbance immunity, endurance, and data retention are addressed and evaluated by using a 64 Mb PRAM with 0.12 /spl mu/m technology. Moreover, observed degradation modes and underlying physical mechanisms are investigated.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128629900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Choi, R. Harris, B. Lee, C. Young, J. Sim, K. Matthews, M. Pendley, G. Bersuker
{"title":"Threshold voltage instability of HfSiO dielectric MOSFET under pulsed stress","authors":"R. Choi, R. Harris, B. Lee, C. Young, J. Sim, K. Matthews, M. Pendley, G. Bersuker","doi":"10.1109/RELPHY.2005.1493179","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493179","url":null,"abstract":"The effects of on-time, off-time, and rise/fall time of AC stress on V/sub th/ shift in HfSiO gate dielectric NMOSFETs have been studied for pulsed stress reliability testing of high-k devices. In slow rise/fall time conditions, charge trapping is only dependent on the sum of on-times. However, as the rise/fall time becomes shorter, a significantly increased charge trapping has been detected. This charging behavior becomes more effective at higher frequency. For the relaxation during off-time to be effective, a longer time than 10/sup - 1/ sec is required. As a result of the relaxation test, it is suggested that charge redistribution would occur during on-time due to the applied field. Therefore, the relaxation would be harder in the sample stressed longer because the distribution of charge traps is more stable.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"14 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113967871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J.F. Chen, Kuo-Ming Wu, Kaung-Wan Lin, Y. Su, S. Hsu
{"title":"Hot-carrier reliability in submicrometer 40V LDMOS transistors with thick gate oxide","authors":"J.F. Chen, Kuo-Ming Wu, Kaung-Wan Lin, Y. Su, S. Hsu","doi":"10.1109/RELPHY.2005.1493148","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493148","url":null,"abstract":"The hot-carrier reliability in thick gate oxide LDMOS transistors is presented for the first time and two distinct behaviors are found. First, higher V/sub gs/ stressing results in a greater degradation because of the Kirk effect. Second, AC lifetime is much longer than DC lifetime because of the recovery in degradation.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114833251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}