Physical mechanism of high resistance of tungsten plug as a root cause of low yield and reliability issue in deep-sub-micron Si technology

Abstract

In current ULSI devices, interconnects serve an important role in enabling multilayer design and fabrication. Tungsten (W) plug processing is a common solution. The W plug resistance is critical to maintain circuit performance and reliability. Abnormal resistance can cause voltage drop and capacitance increase, which, in turn, results in longer signal propagation delay that leads to an undesirable outcome. It becomes worse with increasing interconnection complexity and operating frequency. The high via resistance failure mechanism was investigated and the impact of via etching and post-etch treatment processes were analyzed. Experimental results suggest that via etching introduces a fluorine-containing polymer residue at the via bottom. Both the polymer residue and its reaction product, AlF/sub 3/, could result in a high resistance connection. The subsequent post-etch cleaning is quite critical to assure low resistance interconnections. By optimizing the etching condition and adding lamp de-gas and vacuum bake, the accumulation of F at the via bottom was reduced and via performance was improved.