钨塞高电阻的物理机理是深亚微米硅工艺低成品率和可靠性问题的根源

W. Zhang, K. T. Tan
{"title":"钨塞高电阻的物理机理是深亚微米硅工艺低成品率和可靠性问题的根源","authors":"W. Zhang, K. T. Tan","doi":"10.1109/RELPHY.2005.1493172","DOIUrl":null,"url":null,"abstract":"In current ULSI devices, interconnects serve an important role in enabling multilayer design and fabrication. Tungsten (W) plug processing is a common solution. The W plug resistance is critical to maintain circuit performance and reliability. Abnormal resistance can cause voltage drop and capacitance increase, which, in turn, results in longer signal propagation delay that leads to an undesirable outcome. It becomes worse with increasing interconnection complexity and operating frequency. The high via resistance failure mechanism was investigated and the impact of via etching and post-etch treatment processes were analyzed. Experimental results suggest that via etching introduces a fluorine-containing polymer residue at the via bottom. Both the polymer residue and its reaction product, AlF/sub 3/, could result in a high resistance connection. The subsequent post-etch cleaning is quite critical to assure low resistance interconnections. By optimizing the etching condition and adding lamp de-gas and vacuum bake, the accumulation of F at the via bottom was reduced and via performance was improved.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"67 10","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Physical mechanism of high resistance of tungsten plug as a root cause of low yield and reliability issue in deep-sub-micron Si technology\",\"authors\":\"W. Zhang, K. T. Tan\",\"doi\":\"10.1109/RELPHY.2005.1493172\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In current ULSI devices, interconnects serve an important role in enabling multilayer design and fabrication. Tungsten (W) plug processing is a common solution. The W plug resistance is critical to maintain circuit performance and reliability. Abnormal resistance can cause voltage drop and capacitance increase, which, in turn, results in longer signal propagation delay that leads to an undesirable outcome. It becomes worse with increasing interconnection complexity and operating frequency. The high via resistance failure mechanism was investigated and the impact of via etching and post-etch treatment processes were analyzed. Experimental results suggest that via etching introduces a fluorine-containing polymer residue at the via bottom. Both the polymer residue and its reaction product, AlF/sub 3/, could result in a high resistance connection. The subsequent post-etch cleaning is quite critical to assure low resistance interconnections. By optimizing the etching condition and adding lamp de-gas and vacuum bake, the accumulation of F at the via bottom was reduced and via performance was improved.\",\"PeriodicalId\":320150,\"journal\":{\"name\":\"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.\",\"volume\":\"67 10\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-04-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RELPHY.2005.1493172\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RELPHY.2005.1493172","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

在当前的ULSI器件中,互连在实现多层设计和制造方面起着重要作用。钨(W)插头加工是一种常见的解决方案。插头电阻W对保持电路性能和可靠性至关重要。电阻异常会引起电压下降和电容增加,从而导致信号传播延迟变长,从而导致不良后果。随着互连复杂性和工作频率的增加,这种情况越来越严重。研究了高通孔电阻失效机理,并分析了通孔刻蚀和后刻蚀工艺的影响。实验结果表明,通过蚀刻在通过底部引入了含氟聚合物残留物。聚合物残渣及其反应产物AlF/sub - 3/均可形成高电阻连接。随后的蚀刻后清洗是相当关键的,以确保低电阻互连。通过优化蚀刻条件,加入灯脱气和真空烘烤,减少了F在通孔底部的积累,提高了通孔性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Physical mechanism of high resistance of tungsten plug as a root cause of low yield and reliability issue in deep-sub-micron Si technology
In current ULSI devices, interconnects serve an important role in enabling multilayer design and fabrication. Tungsten (W) plug processing is a common solution. The W plug resistance is critical to maintain circuit performance and reliability. Abnormal resistance can cause voltage drop and capacitance increase, which, in turn, results in longer signal propagation delay that leads to an undesirable outcome. It becomes worse with increasing interconnection complexity and operating frequency. The high via resistance failure mechanism was investigated and the impact of via etching and post-etch treatment processes were analyzed. Experimental results suggest that via etching introduces a fluorine-containing polymer residue at the via bottom. Both the polymer residue and its reaction product, AlF/sub 3/, could result in a high resistance connection. The subsequent post-etch cleaning is quite critical to assure low resistance interconnections. By optimizing the etching condition and adding lamp de-gas and vacuum bake, the accumulation of F at the via bottom was reduced and via performance was improved.
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