2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.最新文献

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The influence of the package environment on the functioning and reliability of RF-MEMS switches 封装环境对RF-MEMS开关功能和可靠性的影响
W. M. van Spengen, P. Czarnecki, R. Puers, J. V. van Beek, I. De Wolf
{"title":"The influence of the package environment on the functioning and reliability of RF-MEMS switches","authors":"W. M. van Spengen, P. Czarnecki, R. Puers, J. V. van Beek, I. De Wolf","doi":"10.1109/RELPHY.2005.1493108","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493108","url":null,"abstract":"This paper discusses the influence of pressure and gas inside a package on the functioning and lifetime of capacitive RF-MEMS switches. It is shown that decreasing the pressure strongly influences the switching speed of a switch, but if it becomes too low it causes anomalous vibration effects. When testing at the same pressure, it is shown that the lifetime of the capacitive switches is higher in a nitrogen environment than in ambient air (lab) environment. These effects are attributed to the humidity of the air and its influence on charge trapping in the insulator, resulting in stiction of the switch bridge. It is also shown that this charge is not stable and that the switch recovers when it is not actuated.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127669044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Novel electrical re-connection of very thin fine pitch ball grid array (VFBGA) package for advanced backside fault isolation 超薄细间距球栅阵列(VFBGA)封装的新型电气重新连接,用于先进的背面故障隔离
Li Qian, Yan Xu, Guo-Zheng Song, Xiaoyu Ji
{"title":"Novel electrical re-connection of very thin fine pitch ball grid array (VFBGA) package for advanced backside fault isolation","authors":"Li Qian, Yan Xu, Guo-Zheng Song, Xiaoyu Ji","doi":"10.1109/RELPHY.2005.1493169","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493169","url":null,"abstract":"With the development of the semiconductor industry, the layers of metal interconnection have increased, and the front-side package dimensions have shrunk. All these trends emphasize the importance of backside fault isolation (FI) in advanced product failure analysis (FA). However, electrical signal re-connection when handling the repackage becomes the primary challenge in handling backside FA. An innovative method for electrical re-connection, which can be effectively applied to the very thin fine pitch ball grid array (VFBGA) package for backside FI, is introduced. By engraving a pattern (for example holes, blocks and trenches) on the surface of the package, and depositing metal into the pattern, electrical signals can be re-connected out from bond pads to metal blocks on the package surface through metal lines embedded in the pattern. Detailed processes, operating parameters and experimental results are represented.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127681054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reliability issues associated with operating voltage constraints in advanced SiGe HBTs 高级SiGe hbt中与工作电压限制相关的可靠性问题
C. Grens, J. Cressler, J. Andrews, Q. Liang, A. Joseph
{"title":"Reliability issues associated with operating voltage constraints in advanced SiGe HBTs","authors":"C. Grens, J. Cressler, J. Andrews, Q. Liang, A. Joseph","doi":"10.1109/RELPHY.2005.1493121","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493121","url":null,"abstract":"The paper addresses many aspects of the relationship between operating voltage constraints and reliability issues in SiGe HBTs, examining breakdown-related instabilities as they relate to technology generation, device geometry, bias configuration, and operating current density. New definitions for breakdown voltage, adopted from standard measurements, are presented. Practical design and reliability implications of breakdown are explored through careful measurement and simulation using quasi-3D compact models. Overall, SiGe HBTs; biased in common-base configuration and driven by constant emitter current, are shown to possess higher stable operating voltage limits than those biased in a common-emitter configuration and driven by constant base current. However, biasing beyond the determined \"safe-operating-area\" can result in impedance matching and linearity issues at lower currents and significant increases in hot-carrier degradation at higher currents, and must be carefully considered from a circuit design perspective.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132379398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Change of acceleration behavior of time-dependent dielectric breakdown by the BEOL process: indications for hydrogen induced transition in dominant degradation mechanism BEOL过程中随时间介电击穿加速行为的变化:主要降解机制中氢诱导转变的指示
T. Pompl, K. Allers, R. Schwab, K. Hofmann, M. Röhner
{"title":"Change of acceleration behavior of time-dependent dielectric breakdown by the BEOL process: indications for hydrogen induced transition in dominant degradation mechanism","authors":"T. Pompl, K. Allers, R. Schwab, K. Hofmann, M. Röhner","doi":"10.1109/RELPHY.2005.1493118","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493118","url":null,"abstract":"One single modification in the back end of line (BEOL) process can change the acceleration behavior of time-dependent dielectric breakdown (TDDB). It is demonstrated that two competing degradation mechanisms exist in parallel, which follow time dependences according to the E-model and the 1/E-model. Negative bias temperature instability (NBTI) tests correlate well with TDDB results. A continuous hydrogen reaction model is introduced, which can explain the experimental results.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130906230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
The effect of mechanical stress from stopping nitride to the reliability of tunnel oxide and data retention characteristics of NAND FLASH memory 停止氮化的机械应力对隧道氧化物可靠性和NAND闪存数据保留特性的影响
J. Om, Eun-seok Choi, Se-Jun Kim, Heegee Lee, Y. Kim, Heehyun Chang, Sung-Ki Park, G. Bae
{"title":"The effect of mechanical stress from stopping nitride to the reliability of tunnel oxide and data retention characteristics of NAND FLASH memory","authors":"J. Om, Eun-seok Choi, Se-Jun Kim, Heegee Lee, Y. Kim, Heehyun Chang, Sung-Ki Park, G. Bae","doi":"10.1109/RELPHY.2005.1493094","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493094","url":null,"abstract":"One of the most important characteristics of NAND FLASH memory is data retention. Data retention characteristics depends on the reliability of tunnel oxide under constant current (F/N) stress with respect to defects such as interface states and defects responsible for SILC (stress-induced-leakage-current). Even though the reliability of tunnel oxide is determined by tunnel oxidation itself, various subsequent processes also can influence it. Here, we want to report the impact of mechanical stress on stopping nitride, which is used as an etch stopper, on the reliability of tunnel oxide and data retention characteristics.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131115628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Mechanism of drain disturb in SONOS flash EEPROMs SONOS闪存eeprom的漏极干扰机理
P.B. Kumar, R. Sharma, P. Nair, D. Nair, S. Kamohara, S. Mahapatra, J. Vasi
{"title":"Mechanism of drain disturb in SONOS flash EEPROMs","authors":"P.B. Kumar, R. Sharma, P. Nair, D. Nair, S. Kamohara, S. Mahapatra, J. Vasi","doi":"10.1109/RELPHY.2005.1493082","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493082","url":null,"abstract":"We investigate the mechanism of drain disturb in SONOS flash memory cells. Our results show that drain disturb can be a serious concern in a programmed state and is caused by injection of holes from the substrate into the nitride. We identify the key factors responsible for this to be band-to-band tunneling at the drain junction and impact ionization of the channel leakage current.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131680880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Effects of post metallization annealing on the electrical reliability of ultra-thin HfO/sub 2/ films with MoN and WN gate electrodes 金属化后退火对单晶硅和氮化硅栅极超薄HfO/sub /薄膜电可靠性的影响
S. Chatterjee, Y. Kuo, J. Lu, J. Tewg, P. Majhi
{"title":"Effects of post metallization annealing on the electrical reliability of ultra-thin HfO/sub 2/ films with MoN and WN gate electrodes","authors":"S. Chatterjee, Y. Kuo, J. Lu, J. Tewg, P. Majhi","doi":"10.1109/RELPHY.2005.1493175","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493175","url":null,"abstract":"Aggressive scaling of CMOS devices for submicron technology has enabled the exponential growth of MOSFETs in complexity and functionality over the past decades. HfO/sub 2/ films have been shown to be promising high-k candidates. Among refractory metal nitrides, WN and MoN are the promising candidates for gate electrode materials because of their excellent diffusion barrier properties and high melting points. The origin of traps in high-k dielectrics, however, still remains a question. When an electron current is passed through the HfO/sub 2/ of a MOS capacitor, defects such as electron traps, interface states, etc., gradually build up in the oxide. The stress induced leakage current (SILC) is correlated with the tunneling current through the oxide layer during electrical stress. A conductive path is created in the gate oxide layer after reaching a critical trap density, called soft breakdown (SBD). Then, the Joule heating in the local conductive path leads to lateral propagation of the leakage spots and the oxide is finally broken down, i.e. hard breakdown (HBD). The present work is focused on the electrical reliability aspects of different gate electrodes (MoN and WN) with ultra thin HfO/sub 2/ (5 nm) for MOS capacitor fabrication.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133745673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Hot carrier degradation of lateral DMOS transistor capacitance and reliability issues 热载流子退化的横向DMOS晶体管电容和可靠性问题
N. Hefyene, C. Anghel, Renaud Gillon, Zeee, Adrian M. Ionescu, Member, '. Swiss
{"title":"Hot carrier degradation of lateral DMOS transistor capacitance and reliability issues","authors":"N. Hefyene, C. Anghel, Renaud Gillon, Zeee, Adrian M. Ionescu, Member, '. Swiss","doi":"10.1109/RELPHY.2005.1493146","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493146","url":null,"abstract":"This paper reports on an experimental evaluation of the hot-carrier impact on capacitances of high voltage DMOS transistors and their correlation with the degradation of DC characteristics. Two stress conditions were selected: (i) stress-A: at maximum drain voltage (near breakdown) and a gate voltage providing maximum body-current, I/sub Bmax/, and; (ii) stress-B: at maximum drain and gate voltages, which are the most relevant for device reliability. The proposed investigations experimentally distinguish among drift-region degradation, for stress-A, and gate oxide degradation near the source-end, for stress-B. In the case of stress-B, while traditional DC evaluation of stress impact suggests a significant shift in the DC parameters, the DMOS AC characteristics appear considerably altered. This suggests the importance of the systematic experimental evaluation of the impact of hot-carrier degradation of AC characteristics and its correlation with DC degradation in order to explain the degradation mechanisms.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114367820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Reliability assessment of discrete-trap memories for NOR applications NOR应用中离散陷阱存储器的可靠性评估
C. M. Compagnoni, D. Ielmini, A. Spinelli, A. Lacaita, R. Sotgiul
{"title":"Reliability assessment of discrete-trap memories for NOR applications","authors":"C. M. Compagnoni, D. Ielmini, A. Spinelli, A. Lacaita, R. Sotgiul","doi":"10.1109/RELPHY.2005.1493091","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493091","url":null,"abstract":"We provide an experimental and theoretical investigation of the reliability properties of discrete-trap memories in view of their application in the NOR architecture. Charge localization at the junction edges after channel hot-electron injection is studied using bake-accelerated retention tests on both nitride and nanocrystal memory cells. Vertical and lateral charge migrations are shown to be responsible for the threshold voltage loss for both small and large reading drain voltages. Drain disturb is shown to be comparable to state-of-art flash cells, while highly improved drain turn on immunity is shown for both nanocrystal and nitride cells.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117137635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Study of factors limiting ESD diode performance in 90nm CMOS technologies and beyond 90nm及以上CMOS技术中限制ESD二极管性能的因素研究
K. Chatty, R. Gauthier, C. Putnam, M. Muhammad, M. Woo, J. Li, R. Halbach, C. Seguin
{"title":"Study of factors limiting ESD diode performance in 90nm CMOS technologies and beyond","authors":"K. Chatty, R. Gauthier, C. Putnam, M. Muhammad, M. Woo, J. Li, R. Halbach, C. Seguin","doi":"10.1109/RELPHY.2005.1493070","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493070","url":null,"abstract":"The on-resistance and failure current of electrostatic discharge (ESD) protection diodes in 90 nm and 65 nm bulk CMOS technologies is determined largely by the resistance and failure of metal lines, contacts or vias. With design optimization, P/sup +//N-well ESD diodes fabricated in a 90 nm bulk CMOS technology achieved a forward voltage drop of 1.66 V at 2 A, an on-resistance of 0.27 /spl Omega/ and a 100 ns TLP failure current greater than 5 A with a junction capacitance of only 125 fF, area of 330 /spl mu/m/sup 2/ and anode perimeter of 300 /spl mu/m.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129406970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
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