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2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.最新文献

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Charge trapping by oxygen-related defects in HfO/sub 2/-based high-k gate dielectrics [MOSFETs] HfO/ sub2 /基高k栅极电介质中氧相关缺陷的电荷捕获
2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493186
K. Yamabe, M. Goto, K. Higuchi, A. Uedono, K. Shiraishi, S. Miyazaki, K. Torii, M. Boero, T. Chikyow, S. Yamasaki, H. Kitajima, K. Yamada, T. Arikado
{"title":"Charge trapping by oxygen-related defects in HfO/sub 2/-based high-k gate dielectrics [MOSFETs]","authors":"K. Yamabe, M. Goto, K. Higuchi, A. Uedono, K. Shiraishi, S. Miyazaki, K. Torii, M. Boero, T. Chikyow, S. Yamasaki, H. Kitajima, K. Yamada, T. Arikado","doi":"10.1109/RELPHY.2005.1493186","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493186","url":null,"abstract":"The time-dependences of leakage currents due to electrons and holes flowing through HfO/sub 2/-based high-k gate dielectric films under constant voltage stresses are investigated by a carrier separation method using field-effect transistor structures. In the case of balanced injection, some of the injected electrons were trapped near the gate, while some of the injected holes were trapped near the substrate. As a result, both leakage currents reduced. Capacitance change during the relaxation after the removal of the gate voltage stress supported the leakage current change. The relationship between the electron-/hole-trapping centers and oxygen-related defects in high-k dielectric films is discussed.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128317716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Reliability considerations of strained silicon on relaxed silicon-germanium (SiGe) substrate 应变硅在松弛硅锗(SiGe)衬底上的可靠性考虑
2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493120
J. Shih, K. Wu
{"title":"Reliability considerations of strained silicon on relaxed silicon-germanium (SiGe) substrate","authors":"J. Shih, K. Wu","doi":"10.1109/RELPHY.2005.1493120","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493120","url":null,"abstract":"The process-induced I-V characteristics and reliability degradations for both nMOSFETs and pMOSFETs on strained Si have been fully characterized. Contrary to nMOSFETs, an apparent device reliability degradation of pMOSFETs at high temperature was observed. The degradation mechanism is attributed to SiGe substrate-induced donor-type interface state generation along the oxide/Si interface. From a manufacturing point of view, it is considered that not only the strain-induced misfit dislocations but also the MOSFETs' reliability degradations should be considered for strained-Si technology with SiGe substrate.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129661508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Effect of STI shape and tunneling oxide thinning on cell Vth variation in the flash memory STI形状和隧道氧化物减薄对快闪存储器中电池Vth变化的影响
2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493197
JaiDong Lee, Junghwan Kim, Woong Lee, Sanghoon Lee, H. Lim, Jaeduk Lee, S. Nam, Hyeon-deok Lee, Chang-Lyong Song
{"title":"Effect of STI shape and tunneling oxide thinning on cell Vth variation in the flash memory","authors":"JaiDong Lee, Junghwan Kim, Woong Lee, Sanghoon Lee, H. Lim, Jaeduk Lee, S. Nam, Hyeon-deok Lee, Chang-Lyong Song","doi":"10.1109/RELPHY.2005.1493197","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493197","url":null,"abstract":"We studied factors which affect cell Vth variation in the floating gate flash memory. By simulation and experiment, we showed that the shape of STI (shallow trench isolation) and the tunnel oxide thickness in the STI edge were the main control factors. For example, sharp and thin oxide in the STI edge caused an uncontrolled F-N gate current in the program or erase operation, which directly indicated the amount of threshold voltage in the flash memory. Furthermore, we found that tunnel oxide thinning was closely related to the activation energy in the oxidation process. Smaller activation energy resulted in better thinning and better cell Vth distribution.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130022267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
The dielectric material dependence of stress and stress relaxation on the mechanism of stress-voiding of Cu interconnects 应力和应力松弛对Cu互连体应力消除机制的介电材料依赖性
2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493084
Jong-Min Paik, Jung-Kyu Jung, Young‐Chang Joo
{"title":"The dielectric material dependence of stress and stress relaxation on the mechanism of stress-voiding of Cu interconnects","authors":"Jong-Min Paik, Jung-Kyu Jung, Young‐Chang Joo","doi":"10.1109/RELPHY.2005.1493084","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493084","url":null,"abstract":"The line width dependence of stress in damascene Cu was examined experimentally as well as with a numerical simulation. The measured hydrostatic stress was found to increase with increasing line width. The larger stress in an interconnect with large dimension is attributed to the larger grain size, which induces higher growth stress in addition to thermomechanical stress. A stress model based on microstructure was constructed and the contribution of the growth and thermal stress of the damascene lines were quantified using finite element analysis. It was found that the stress of the via is lower than that of wide lines when both the growth stress and thermal stress were considered. Therefore, the characteristic failure mode, i.e. voiding in a via neighboring a wide line, was successfully explained by our stress model.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129071331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Influence of gate material and stress voltage on post breakdown leakage current of high k dielectrics 栅极材料和应力电压对高k介电材料击穿后漏电流的影响
2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493178
R. Duschl, M. Kerber, U. Schroeder, T. Hecht, S. Jakschik, C. Kapteyn, S. Kudelka
{"title":"Influence of gate material and stress voltage on post breakdown leakage current of high k dielectrics","authors":"R. Duschl, M. Kerber, U. Schroeder, T. Hecht, S. Jakschik, C. Kapteyn, S. Kudelka","doi":"10.1109/RELPHY.2005.1493178","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493178","url":null,"abstract":"The breakdown (BD) behaviour of Al/sub 2/O/sub 3/ dielectrics is investigated as a function of electrode material, stress voltage and thickness. Other than generally reported in the literature, two stable BD phases were found, even for metal electrodes, which is attributed to finite threshold energy for hard BD formation. This results in a limitation of the post BD current at product operation conditions and therefore opens up possibilities for target relaxation.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130494056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Significance of including substrate capacitance in the full chip circuit model of ICs under CDM stress CDM应力下集成电路全片电路模型中包含衬底电容的意义
2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493166
M. Sowariraj, P. de Jong, S.M. Cora, T. Smedes, A. Mouthaan, F. Kuper
{"title":"Significance of including substrate capacitance in the full chip circuit model of ICs under CDM stress","authors":"M. Sowariraj, P. de Jong, S.M. Cora, T. Smedes, A. Mouthaan, F. Kuper","doi":"10.1109/RELPHY.2005.1493166","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493166","url":null,"abstract":"In the CDM type of ESD, the IC is both the source and part of the discharge current path. To study the CDM performance of an IC, a full-chip circuit model that includes the various static charge sources and its discharge path through the circuit as it occurs in reality is needed. Static charge sources in a CDM event are the various package capacitors. CDM circuit models presented before include only the capacitors formed by the IC circuit design on the package and not the capacitance of the die attachment plate on which the die is placed. The paper emphasizes the need to include this capacitance and presents a simple method of including this capacitor and its discharge path through the circuit during CDM stress.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125437167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Comparison of NMOS and PMOS stress for determining the source of NBTI in TiN/HfSiON devices [MOSFETs] 测定TiN/HfSiON器件[mosfet]中NBTI源的NMOS和PMOS应力比较
2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493067
H. Harris, R. Choi, B. Lee, C. Young, J. Sim, K. Mathews, P. Zeitzoff, P. Majhi, G. Bersuker
{"title":"Comparison of NMOS and PMOS stress for determining the source of NBTI in TiN/HfSiON devices [MOSFETs]","authors":"H. Harris, R. Choi, B. Lee, C. Young, J. Sim, K. Mathews, P. Zeitzoff, P. Majhi, G. Bersuker","doi":"10.1109/RELPHY.2005.1493067","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493067","url":null,"abstract":"The evaluation of the instability of the threshold voltage in high-k gate stack structures is of paramount importance in assessing the reliability of next generation FETs. In the case of SiO/sub 2/ gate dielectric PMOS transistors, this instability, known as NBTI, has been attributed to the hole-assisted dissociation of the hydrogen that passivates dangling bonds at the interface with the Si substrate. However, in hafnium-based gate stacks, evaluation of the NBTI phenomenon is complicated by the charge trapping process, which was shown to occur reversibly on pre-existing defects in NMOS devices. In this report, we examine the cycle dependence of negative gate stress and positive gate de-trapping on PMOS high-k/metal gate transistors. The threshold voltage instability is found to be due mainly to charge trapping and de-trapping of both shallow and deep electron traps in the high-k dielectric. There is minimal change in the interface quality with negative bias stress, and a similar detrapping nature is found for NMOS devices with a comparable electric field.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123366521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Degradation of electromigration lifetime by post-annealing for Cu/low-k interconnects Cu/低k互连后退火对电迁移寿命的影响
2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493190
Y. Kakuhara, K. Ueno
{"title":"Degradation of electromigration lifetime by post-annealing for Cu/low-k interconnects","authors":"Y. Kakuhara, K. Ueno","doi":"10.1109/RELPHY.2005.1493190","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493190","url":null,"abstract":"Cu/low-k interconnects are widely used for 130 nm-node LSIs and beyond, and their electromigration (EM) reliability has been reported. The effects of annealing after Cu plating on the EM reliability and Cu film characteristics such as post-CMP defects have been studied previously. However, the effects of thermal processes after forming interconnect structures are somewhat missing. In the fabrication of multilevel interconnects, the lower level interconnects are annealed many times during the thermal processes for the upper level interconnects. So, it is important to forecast the EM lifetime taking the influence of total thermal processes into consideration. But few works have been reported. In this study, we evaluate the influence of post-annealing on EM reliability. Results indicate that EM lifetime was degraded by post-annealing packaged samples, and it is suggested that EM lifetime for lower level interconnects potentially degrades by thermal processes during multilevel interconnect fabrication.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122332037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Estimating DPPM during the prototype to product ramp phase [IC example] 从原型到产品斜坡阶段的DPPM估算[IC示例]
2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493203
T.J. Anderson
{"title":"Estimating DPPM during the prototype to product ramp phase [IC example]","authors":"T.J. Anderson","doi":"10.1109/RELPHY.2005.1493203","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493203","url":null,"abstract":"A process allowing one to estimate the early failure rate and subsequent defective PPM for a product's use is presented. Keys points for early technology implementation are a limited sample size, identifying and assessing the impact of a failure distribution, determining a defect Pareto, de-rating to product use, test screen modifications or process iterations needed for further improvements and any applicable burn in duration.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116127698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Evaluation on efficient measurement setup for transient-induced latchup with bi-polar trigger [CMOS IC reliability] 双极触发瞬态闭锁有效测量装置评价[CMOS IC可靠性]
2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493073
M. Ker, Sheng-Fu Hsu
{"title":"Evaluation on efficient measurement setup for transient-induced latchup with bi-polar trigger [CMOS IC reliability]","authors":"M. Ker, Sheng-Fu Hsu","doi":"10.1109/RELPHY.2005.1493073","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493073","url":null,"abstract":"An efficient measurement setup for transient-induced latchup (TLU) with bi-polar trigger is evaluated in this paper. The influences of the current-blocking diode and the current-limiting resistance on TLU immunity are investigated with a silicon controlled rectifier (SCR) fabricated in a 0.25-/spl mu/m CMOS technology. The measurement setup without a current-blocking diode but with a small current-limiting resistance is recommended to evaluate TLU immunity of CMOS ICs. This recommended measurement setup not only can accurately judge the TLU level of the CMOS ICs without over estimation, but also is beneficial in avoiding electrical over-stress (EOS) damage on the device under test (DUT). To further prove the utility of this recommended TLU measurement in real circuits, a ring oscillator fabricated in 0.25-/spl mu/m CMOS technology is used as the test circuit for verification.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121348664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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