Comparison of NMOS and PMOS stress for determining the source of NBTI in TiN/HfSiON devices [MOSFETs]

Abstract

The evaluation of the instability of the threshold voltage in high-k gate stack structures is of paramount importance in assessing the reliability of next generation FETs. In the case of SiO/sub 2/ gate dielectric PMOS transistors, this instability, known as NBTI, has been attributed to the hole-assisted dissociation of the hydrogen that passivates dangling bonds at the interface with the Si substrate. However, in hafnium-based gate stacks, evaluation of the NBTI phenomenon is complicated by the charge trapping process, which was shown to occur reversibly on pre-existing defects in NMOS devices. In this report, we examine the cycle dependence of negative gate stress and positive gate de-trapping on PMOS high-k/metal gate transistors. The threshold voltage instability is found to be due mainly to charge trapping and de-trapping of both shallow and deep electron traps in the high-k dielectric. There is minimal change in the interface quality with negative bias stress, and a similar detrapping nature is found for NMOS devices with a comparable electric field.