Evaluation on efficient measurement setup for transient-induced latchup with bi-polar trigger [CMOS IC reliability]

An efficient measurement setup for transient-induced latchup (TLU) with bi-polar trigger is evaluated in this paper. The influences of the current-blocking diode and the current-limiting resistance on TLU immunity are investigated with a silicon controlled rectifier (SCR) fabricated in a 0.25-/spl mu/m CMOS technology. The measurement setup without a current-blocking diode but with a small current-limiting resistance is recommended to evaluate TLU immunity of CMOS ICs. This recommended measurement setup not only can accurately judge the TLU level of the CMOS ICs without over estimation, but also is beneficial in avoiding electrical over-stress (EOS) damage on the device under test (DUT). To further prove the utility of this recommended TLU measurement in real circuits, a ring oscillator fabricated in 0.25-/spl mu/m CMOS technology is used as the test circuit for verification.