Significance of including substrate capacitance in the full chip circuit model of ICs under CDM stress

Abstract

In the CDM type of ESD, the IC is both the source and part of the discharge current path. To study the CDM performance of an IC, a full-chip circuit model that includes the various static charge sources and its discharge path through the circuit as it occurs in reality is needed. Static charge sources in a CDM event are the various package capacitors. CDM circuit models presented before include only the capacitors formed by the IC circuit design on the package and not the capacitance of the die attachment plate on which the die is placed. The paper emphasizes the need to include this capacitance and presents a simple method of including this capacitor and its discharge path through the circuit during CDM stress.