2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.最新文献_第4页

Comparison of product failure rate to the component soft error rates in a multi-core digital signal processor 多核数字信号处理器中产品故障率与元件软错误率的比较

2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493086

Xiaowei Zhu, R. Baumann, C. Pilch, J. Zhou, J. Jones, C. Cirba

引用次数: 6

Low frequency noise degradation in ultra-thin oxide (15/spl Aring/) analog n-MOSFETs resulting from valence-band tunneling 超薄氧化物(15/spl)模拟n- mosfet中由价带隧穿引起的低频噪声退化

2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493095

J.W. Wu, J. You, H.C. Ma, C.C. Cheng, C. Hsu, G. Huang, C.S. Chang, Tahui Wang

引用次数: 3

Lifetime study for a poly fuse in a 0.35 /spl mu/m polycide CMOS process 0.35 /spl mu/m多晶CMOS工艺中聚熔断器的寿命研究

2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493126

J. Fellner, P. Boesmueller, H. Reiter

引用次数: 19

A comprehensive solution for ultra-thin oxide reliability issue including a novel explanation of power-law exponent variations [MOSFETs] 超薄氧化物可靠性问题的综合解决方案，包括幂律指数变化的新解释[mosfet]

2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493160

T. Kang, J. Shieh, O. Lo, Ju-ping Chen, Cheng-li Lin, K. Su

引用次数: 1

Dominant SILC mechanisms in HfO/sub 2//TiN gate nMOS and pMOS transistors HfO/sub /TiN栅极nMOS和pMOS晶体管的主要SILC机制

2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493183

S. Krishnan, J. Peterson, C. Young, G. Brown, R. Choi, R. Harris, J. H. Sim, P. Zeitzoff, P. Kirsch, J. Gutt, Hong Jyh Li, K. Matthews, J.C. Lee, B. Lee, G. Bersuker

{"title":"Dominant SILC mechanisms in HfO/sub 2//TiN gate nMOS and pMOS transistors","authors":"S. Krishnan, J. Peterson, C. Young, G. Brown, R. Choi, R. Harris, J. H. Sim, P. Zeitzoff, P. Kirsch, J. Gutt, Hong Jyh Li, K. Matthews, J.C. Lee, B. Lee, G. Bersuker","doi":"10.1109/RELPHY.2005.1493183","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493183","url":null,"abstract":"To introduce high-k dielectrics into conventional CMOS product flow, reliability issues of high-k gate stacks need to be addressed. Although several studies have focused on this issue, the physical mechanism of stress-induced degradation in high-k dielectrics is still not clear. In SiO/sub 2//poly-Si gate stacks, most intrinsic degradations are attributed to trap generation leading to the percolation model type failure, while pre-existing defects are believed to contribute to extrinsic mode failure (Olivio, P. et al., 1988). For the HfO/sub 2//TiN gate stack, it has been reported that a similar mechanism was at work (Crupi, F. et al., 2004). However, considering the high density of pre-existing electron traps (Zhan, N. et al., 2003) and the time dependent reversible threshold voltage shift (Lee, B.H. et al., 2004), one may expect that the electron accumulation in the dielectric during electrical stress may cause the modulation of the energy barrier and affect the electron tunneling, which, in turn, may lead to variation of SILC with the stress time. We have investigate the SILC characteristics of HfO/sub 2//TiN gate nMOS and pMOS transistors in conjunction with the trapping/detrapping processes in the high-k dielectric.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"226 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134577772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Scaling effect on electromigration reliability for Cu/low-k interconnects 铜/低钾互连电迁移可靠性的尺度效应

2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493083

J. Pyun, X. Lu, S. Yoon, N. Henis, K. Neuman, K. Pfeifer, P. Ho

引用次数: 5

Stress migration reliability of wide Cu interconnects with gouging vias 带凿孔的宽铜互连的应力迁移可靠性

2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493085

Y. K. Lim, R. Arijit, K. Pey, C. Tan, C. Seet, T.J. Lee, D. Vigar

{"title":"Stress migration reliability of wide Cu interconnects with gouging vias","authors":"Y. K. Lim, R. Arijit, K. Pey, C. Tan, C. Seet, T.J. Lee, D. Vigar","doi":"10.1109/RELPHY.2005.1493085","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493085","url":null,"abstract":"Stress migration (SM) reliability of wide copper (Cu) interconnects with gouging vias was studied using a via chain structure stressed at temperatures ranging from 150/spl deg/C to 200/spl deg/C. After a 1000-hour SM test, via chain structures at the edge of the wafer were observed to have extremely high resistance due to the formation of stress-induced voids at the silicon nitride (Si/sub 3/N/sub 4/) cap/via interface around the perimeter of the gouging via and at the via bottom. One of the dominant causes for this phenomenon was attributed to the presence of process-induced weak points resulting from poor diffusion barrier layer coverage at the sidewall of the via bottom. In addition, a simulation model based on a three dimensional (3D) finite element analysis (FEA) was developed to study the stress distribution of a gouging via. The simulation results showed that high tensile stress was found at the Si/sub 3/N/sub 4/ cap/via interface around the perimeter of the gouging via. It is believed that at high temperature stressing, the presence of process-induced weak points, coupled with the high tensile stress, favor void nucleation. The steep stress gradient developed around the void vicinity after its nucleation was proposed to be the dominant driving force for subsequent vacancy accumulation and void growth extending beneath the gouging via, thus leading eventually to an open circuit. The effect of via gouging on the SM performance of Cu interconnects was also discussed.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115337507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Direct tunneling stress-induced leakage current in nMOS devices with ultrathin gate oxides 超薄栅极氧化物nMOS器件的直接隧道应力诱发漏电流

2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493159

P. Samanta, T. Y. Man, A. Chan, Qingchun Zhang, Chunxiang Zhu, M. Chan

引用次数: 0

ESD induced damage on ultra-thin gate oxide MOSFETs and its impact on device reliability 超薄栅极氧化mosfet的静电放电损伤及其对器件可靠性的影响

2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493068

A. Cester, S. Gerardin, A. Tazzoli, A. Paccagnella, E. Zanoni, G. Ghidini, G. Meneghesso

引用次数: 7

Determination of the acceleration factor between wafer level and package level electromigration test 晶圆级和封装级电迁移试验加速系数的测定

2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493191

X. Federspiel, D. Ney, V. Girault

{"title":"Determination of the acceleration factor between wafer level and package level electromigration test","authors":"X. Federspiel, D. Ney, V. Girault","doi":"10.1109/RELPHY.2005.1493191","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493191","url":null,"abstract":"The characterization and monitoring of electromigration performance is usually performed using wafer level or package level tests. These two types of test involve very different temperature gradient and current density conditions. These differences of stress condition may affect the determination of electromigration parameters, namely the activation energy, Ea, and the current exponent, n, as described in the empirical Black's law: MTF = A.j/sup -n/exp(Ea/kT). The apparent evolution of n and Ea is critical because it complicates the calculation of extrapolated lifetime. To elucidate this apparent inconsistency, we built a numerical model of the flux of matter in a copper line to simulate lifetime and acceleration factor corresponding to wafer and package level electromigration tests. Our numerical model is able to simulate TTF corresponding to electromigration tests on a wide range of current density (two orders of magnitude). The analysis of simulated TTF predicts that the error in Black's law parameters Ea and n may occur both from wafer level (high current density and Joule heating) and package level (low current density). As a consequence, we recommend taking into consideration temperature gradients as well as the Blech effect to extrapolate lifetime correctly.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123610160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5