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2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs最新文献

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1 cell boost-up converter with ultra low stand-by current 具有超低待机电流的1单元升压转换器
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239753
H. Suzuki, H. Kobayashi, J. Knight
{"title":"1 cell boost-up converter with ultra low stand-by current","authors":"H. Suzuki, H. Kobayashi, J. Knight","doi":"10.1109/WCT.2004.239753","DOIUrl":"https://doi.org/10.1109/WCT.2004.239753","url":null,"abstract":"This paper presents the design of a boost converter which is highly optimized for battery-operated portable systems. This converter employs two different architectures. One is an advanced gated oscillator architecture which achieves 80% efficiency at 100 /spl mu/A output current. Another quasi-PWM mode is based on an adaptive constant on-time architecture, but it enables a constant switching frequency at heavy output load. By selecting one of these two architectures, according to the output load, high efficiency and good regulation are achieved.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132714172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
7 to 30V state-of-art power device implementation in 0.25 /spl mu/m LBC7 BiCMOS-DMOS process technology 7至30V最先进的电源器件实现0.25 /spl mu/m LBC7 BiCMOS-DMOS工艺技术
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240297
S. Pendharkar, R. Pan, Takehito Tamura, B. Todd, T. Efland
{"title":"7 to 30V state-of-art power device implementation in 0.25 /spl mu/m LBC7 BiCMOS-DMOS process technology","authors":"S. Pendharkar, R. Pan, Takehito Tamura, B. Todd, T. Efland","doi":"10.1109/WCT.2004.240297","DOIUrl":"https://doi.org/10.1109/WCT.2004.240297","url":null,"abstract":"The performance of low-to-medium voltage power devices (7 V-30 V) implemented in an advanced 0.25 /spl mu/m BiCMOS-DMOS process is presented. The devices were optimized for a range of applications in this voltage group. In particular, the lateral DMOS devices have a capability of operating with the drain fully isolated from the substrate. The Rsp-BVdss performance for these devices is shown to be very competitive with respect to similar technologies. This performance is achieved without sacrificing the requirements for square electrical and lifetime safe operating area (SOA).","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114913036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
A novel n-channel MOSFET featuring an integrated Schottky and no internal p-n junction 一种新颖的n沟道MOSFET，具有集成肖特基和无内部pn结
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240292
A. Mirchandani, N. Thapar, T. Boden, R. Sodhi, D. Kinzer
{"title":"A novel n-channel MOSFET featuring an integrated Schottky and no internal p-n junction","authors":"A. Mirchandani, N. Thapar, T. Boden, R. Sodhi, D. Kinzer","doi":"10.1109/WCT.2004.240292","DOIUrl":"https://doi.org/10.1109/WCT.2004.240292","url":null,"abstract":"This paper presents a new MOSFET structure with an integrated Schottky junction in every unit cell and with no p-n junction in the current flow path. This eliminates the injected reverse recovery charge while providing a low forward voltage drop anti-parallel Schottky diode. Gate controlled current conduction in the on-state takes place through an accumulated channel region formed along the trench sidewall. A specific on-resistance of 10.6 m/spl Omega/-mm/sup 2/ and 7.6 m/spl Omega/-mm/sup 2/ for a gate bias of 4.5 V and 10V respectively has been achieved, with a forward blocking voltage of over 30 V. This coupled with no reverse recovery charge makes the device very suitable for high frequency DC-DC converter applications.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124404702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Temperature characteristics of a new 100V rated power MOSFET, VLMOS (vertical LOCOS MOS) 新型100V额定功率MOSFET, VLMOS(垂直LOCOS MOS)的温度特性
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239756
M. Kodama, E. Hayashi, Y. Nishibe, T. Uesugi
{"title":"Temperature characteristics of a new 100V rated power MOSFET, VLMOS (vertical LOCOS MOS)","authors":"M. Kodama, E. Hayashi, Y. Nishibe, T. Uesugi","doi":"10.1109/WCT.2004.239756","DOIUrl":"https://doi.org/10.1109/WCT.2004.239756","url":null,"abstract":"In this paper, we proposed a new 100 V rated power MOSFET, called \"VLMOS (vertical LOCOS MOSFET)\", and investigated characteristics of the VLMOS under high temperature. From simulation and experimental results, we verified that it overcame the \"Si limit\" and had superior temperature characteristics in specific on-resistance. This means that the VLMOS is excellent for wide-temperature range operations, especially for automotive applications.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127610151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
RESURF stepped oxide (RSO) MOSFET for 85V having a record-low specific on-resistance resuf阶梯氧化物(RSO) MOSFET 85V具有创纪录的低比导通电阻
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239902
Gerrit Koops, E. Hijzen, R. Hueting, M. in 't Zandt
{"title":"RESURF stepped oxide (RSO) MOSFET for 85V having a record-low specific on-resistance","authors":"Gerrit Koops, E. Hijzen, R. Hueting, M. in 't Zandt","doi":"10.1109/WCT.2004.239902","DOIUrl":"https://doi.org/10.1109/WCT.2004.239902","url":null,"abstract":"A RESURF stepped oxide (RSO) transistor is presented and electrically characterised. The processed RSO MOSFET includes a trench field-plate network in the drift region that is isolated with a thick oxide layer. This trench network has a hexagonal layout that induces an improved RESURF effect at breakdown compared with the more common stripe (2D) layout. Consequently, the effective doping can be two times higher for the hexagonal layout. We have obtained a record value for the specific on-resistance (R/sub ds,on/) of 58 m/spl Omega/.mm/sup 2/ at V/sub gs/=10 V for a breakdown voltage (BV/sub ds/,) of 85 V. These values have been obtained for devices having a 4.0 /spl mu/m cell pitch and a 5 /spl mu/m long drift region with a doping level of 2.10/sup 16/ cm/sup -3/. Measurements of the gate-drain charge density (Q/sub gd/) for these devices show that Q/sub gd/ is fully dominated by the oxide capacitance of the field-plate along the drift region.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129000752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
A 12V complementary RF LDMOS technology developed on a 0.18/spl mu/m CMOS platform 在0.18/spl mu/m CMOS平台上开发了12V互补RF LDMOS技术
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239744
A. Moscatelli, C. Contiero, P. Galbiati, C. Raffaglio
{"title":"A 12V complementary RF LDMOS technology developed on a 0.18/spl mu/m CMOS platform","authors":"A. Moscatelli, C. Contiero, P. Galbiati, C. Raffaglio","doi":"10.1109/WCT.2004.239744","DOIUrl":"https://doi.org/10.1109/WCT.2004.239744","url":null,"abstract":"Complementary RF LDMOS devices have been successfully integrated for the first time in a 0.18 /spl mu/m CMOS platform. A 12 V voltage capability and cut off frequency of 18 GHz and 12 GHz, respectively, for N-channel and P-channel devices have been obtained. In this paper, the complementary RF LDMOS architecture is presented together with device performances.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131336765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Microprocessor voltage regulators and power supply trends and device requirements 微处理器稳压电源的发展趋势和器件要求
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239748
E. Stanford
{"title":"Microprocessor voltage regulators and power supply trends and device requirements","authors":"E. Stanford","doi":"10.1109/WCT.2004.239748","DOIUrl":"https://doi.org/10.1109/WCT.2004.239748","url":null,"abstract":"Summary form only given. This paper gives a general overview of microprocessor power regulators and supplies. Firstly, it covers the CPU power road map, thermal issues, current and voltage scaling and system constraints. Secondly, it outlines system operating parameters. Thirdly, it details buck regulator operation. Finally, it considers system level power supply trends, system chassis shrinking and power supply density.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123243269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Electrical characterisation of vertical vapor phase doped (VPD) RESURF MOSFETs 垂直气相掺杂(VPD) RESURF mosfet的电学特性
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240356
R. van Dalen, C. Rochefort
{"title":"Electrical characterisation of vertical vapor phase doped (VPD) RESURF MOSFETs","authors":"R. van Dalen, C. Rochefort","doi":"10.1109/WCT.2004.240356","DOIUrl":"https://doi.org/10.1109/WCT.2004.240356","url":null,"abstract":"Publications on the optimisation of vertical RESURF MOSFETs typically only address the drift region. The drift region resistance decreases strongly with pitch size, potentially offering extremely low specific resistances when moving to smaller pitch sizes. However, at a certain pitch, one will have decreased the drift region component such that other contributions will start to play a dominant role and need to be taken into account when optimising such devices. Recently, the first vertical RESURF MOSFETs, manufactured using a trench etch and vapor phase doping (VPD) process, were presented with pitch size down to 4 /spl mu/m. Based on the electrical characterisation of these devices, we evaluate the various contributions to the overall specific resistance and their effect on the attainable figure-of-merits (FOMs) of vertical RESURF devices with DMOS layout at such small pitch.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125254169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A double channel normally-off SiC JFET device with ultra-low on-state resistance 一种具有超低导通电阻的双通道常关SiC JFET器件
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240034
F. Udrea, A. Mihaila, S. J. Rashid, G. Amaratunga, Y. Takeuchi, M. Kataoka, R. K. Malhan
{"title":"A double channel normally-off SiC JFET device with ultra-low on-state resistance","authors":"F. Udrea, A. Mihaila, S. J. Rashid, G. Amaratunga, Y. Takeuchi, M. Kataoka, R. K. Malhan","doi":"10.1109/WCT.2004.240034","DOIUrl":"https://doi.org/10.1109/WCT.2004.240034","url":null,"abstract":"In this paper we report a novel 'all-epitaxial' 1.2 kV normally-off JFET featuring a double channel to improve considerably the specific on-state resistance. The device relies on a succession of n and p/sup +/ stripes in the channel/gate region. A 30% reduction in the on-resistance is obtained when compared to a standard single channel normally-off JFET. Depending on the structure considered, the unipolar value of the specific on-state resistance for a 1.2 kV device is below 3 m/spl Omega/cm/sup 2/.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125500735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Switching-self-clamping-mode "SSCM", a breakthrough in SOA performance for high voltage IGBTs and diodes 开关自箝位模式“SSCM”，在高压igbt和二极管的SOA性能上取得突破
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/ISPSD.2004.1332970
Munaf T. A. Rahimo, A. Kopta, S. Eicher, U. Schlapbach, S. Linder
{"title":"Switching-self-clamping-mode \"SSCM\", a breakthrough in SOA performance for high voltage IGBTs and diodes","authors":"Munaf T. A. Rahimo, A. Kopta, S. Eicher, U. Schlapbach, S. Linder","doi":"10.1109/ISPSD.2004.1332970","DOIUrl":"https://doi.org/10.1109/ISPSD.2004.1332970","url":null,"abstract":"In this paper, we present a new high voltage IGBT and diode design platform exhibiting the highest SOA limits achieved to date. We demonstrate for the first time, low loss IGBT and diode chip-sets with voltage ratings ranging from 3.3 kV to 6.5 kV, capable of withstanding both dynamic avalanche and what we refer to as the switching-self-clamping-mode; hence, resulting in a clear breakthrough in SOA capability for high voltage devices.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121190049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 67
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