垂直气相掺杂(VPD) RESURF mosfet的电学特性

R. van Dalen, C. Rochefort
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引用次数: 10

摘要

关于垂直复用mosfet优化的出版物通常只涉及漂移区域。漂移区电阻随着螺距尺寸的增大而减小,当移动到较小的螺距尺寸时,可能会提供极低的比电阻。然而,在一定的音高下,人们会减少漂移区分量,这样其他贡献将开始发挥主导作用,并且在优化此类设备时需要考虑到这一点。最近,采用沟槽蚀刻和气相掺杂(VPD)工艺制造的第一个垂直RESURF mosfet,其节距尺寸降至4 /spl mu/m。基于这些器件的电气特性,我们评估了对总体比电阻的各种贡献,以及它们对在如此小间距下具有DMOS布局的垂直复用器件可获得的优点系数(FOMs)的影响。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Electrical characterisation of vertical vapor phase doped (VPD) RESURF MOSFETs
Publications on the optimisation of vertical RESURF MOSFETs typically only address the drift region. The drift region resistance decreases strongly with pitch size, potentially offering extremely low specific resistances when moving to smaller pitch sizes. However, at a certain pitch, one will have decreased the drift region component such that other contributions will start to play a dominant role and need to be taken into account when optimising such devices. Recently, the first vertical RESURF MOSFETs, manufactured using a trench etch and vapor phase doping (VPD) process, were presented with pitch size down to 4 /spl mu/m. Based on the electrical characterisation of these devices, we evaluate the various contributions to the overall specific resistance and their effect on the attainable figure-of-merits (FOMs) of vertical RESURF devices with DMOS layout at such small pitch.
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