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Selective growth of ZnO nanowires by employing voltage-assisted hydrothermal growth technique 电压辅助水热生长技术对ZnO纳米线的选择性生长
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032869
Sandip Bhattacharya, S. Mandal, Debopam Bhattacharya, R. Saha, S. Chattopadhyay
{"title":"Selective growth of ZnO nanowires by employing voltage-assisted hydrothermal growth technique","authors":"Sandip Bhattacharya, S. Mandal, Debopam Bhattacharya, R. Saha, S. Chattopadhyay","doi":"10.1109/EDKCON56221.2022.10032869","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032869","url":null,"abstract":"In this work, a novel voltage-assisted double-step chemical bath deposition technique is developed for the controllable selective growth of ZnO nanowires on conducting surface. The impact of voltage-induced electric field on the growth of ZnO NW is investigated from the fundamental understanding of hydrothermal growth kinetics. It is identified that the selective growth of ZnO nanostructures depend upon the electrical field-induced attraction force on Zn2+ and OH- complexes, present in the precursor solution. The morphology and vertical alignment of such voltage-assisted grown nanowires at desirable positions of the substrate are examined by FESEM images. Chemical stoichiometry of the grown nanowires at different positions of the substrate is investigated by performing EDAX. The EDAX plots and the relevant atomic Zn:O ratio indicate the impact of electric field on the hydrothermal technique resulting to the voltage-dependent selective growth of ZnO nanowires.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"315 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115222687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Investigation of the Efficiency of CsGeI3-based solar cell using SCAPS-1D modeling and simulation 基于SCAPS-1D建模与仿真的csgei3基太阳能电池效率研究
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032870
Abhijit Das, D. P. Samajdar, Babban Kumar Ravidas
{"title":"Investigation of the Efficiency of CsGeI3-based solar cell using SCAPS-1D modeling and simulation","authors":"Abhijit Das, D. P. Samajdar, Babban Kumar Ravidas","doi":"10.1109/EDKCON56221.2022.10032870","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032870","url":null,"abstract":"This paper proposes a fully lead (Pb)-free CsGeI<inf>3</inf>-based Perovskite Solar Cell (PSC) modeled and simulated using Solar cell Capacitance Simulator-1D (SCAPS-1D). With this heterojunction structure, an improved power conversion efficiency (PCE) of about 19.30% has been obtained. PCBM and P3HT are used as electron transfer layer (ETL) and hole transfer layer (HTL) respectively. The effect of change of acceptor density and defect density with the absorber layer thickness has been studied theoretically in this paper. The optimized thickness of the absorber layer is found out to be 1.4 and best values of photovoltaic parameters are obtained for an acceptor density of 5×10<sup>17</sup> cm<sup>-3</sup> and defect density of 10<sup>14</sup> cm<sup>-3</sup>. The final photovoltaic performance for the solar cell structure of glass/FTO/PCBM/CsGeI<inf>3</inf>/P3HT/Ag are as follow: J<inf>SC</inf> = 25 mA/cm<sup>2</sup>, V<inf>OC</inf> = 1.060 V, PCE = 19.30%, FF = 87.40%.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"362 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115281108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Diminished Short Channel Effects (SCEs) in Junction Less Double Gate (JL DG) MOSFET 无结双栅MOSFET中减小短沟道效应(SCEs)
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032961
Prashant Kumar, Lalit Rai, N. Gupta, Rashmi Gupta
{"title":"Diminished Short Channel Effects (SCEs) in Junction Less Double Gate (JL DG) MOSFET","authors":"Prashant Kumar, Lalit Rai, N. Gupta, Rashmi Gupta","doi":"10.1109/EDKCON56221.2022.10032961","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032961","url":null,"abstract":"An analysis of Junction less DG MOSFET structure using TCAD is presented in this paper. The effect of variation in silicon thickness has been investigated for the JL DG MOSFET. The transconductance of proposed structure has been evaluated for the variation in dielectric constant and oxide thickness. The key metric parameters are evaluated for the JL DG MOSFET. Furthermore, parameters are compared with JL SG MOSFET. The proposed device structure shows an excellent immunity against SCEs. The silicon substrate has been replaced with germanium substrate in JL DG MOSFET and comparison has been carried out. The germanium transistors show a reduction in DIBL.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"32 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123213709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Ultra-Low Power (86 nW) Low-Voltage (0.6 V) Self-Biased Instrumentation Amplifier for Bio-Medical Applications 一种用于生物医学应用的超低功率(86 nW)低压(0.6 V)自偏置仪器放大器
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032969
Koyel Mukherjee, Soumya Pandit, R. Pal
{"title":"An Ultra-Low Power (86 nW) Low-Voltage (0.6 V) Self-Biased Instrumentation Amplifier for Bio-Medical Applications","authors":"Koyel Mukherjee, Soumya Pandit, R. Pal","doi":"10.1109/EDKCON56221.2022.10032969","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032969","url":null,"abstract":"In this article, an operational transconductance amplifier (OTA)-based self-biased, ultra-low power instrumentation amplifier is proposed. The design is performed in SCL 0.18 μm technology under 0.6 V power supply. The total current drawn from the supply is 144 nA, resulting in ultra-low power consumption of 86 nW. The entire circuit is self-biased by an in-built current reference circuit. The instrumentation amplifier produces a fixed gain of 61 dB with unity gain bandwidth of 4.1 KHz and input RMS noise voltage of 2.01 μVrms. The amplifier is aimed for bio-medical applications and is capable of amplifying a signal as low as 0.5 μV with an ultra-low frequency of 1 Hz also, serving the range of even the weakest possible bio-potential signal quite efficiently.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124789695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of a low-power 3rd order notch filter for biomedical applications 生物医学用低功耗三阶陷波滤波器的设计
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032908
Nikhil Sharma, Shashank Jain, K. Sharma, S. Malhotra
{"title":"Design of a low-power 3rd order notch filter for biomedical applications","authors":"Nikhil Sharma, Shashank Jain, K. Sharma, S. Malhotra","doi":"10.1109/EDKCON56221.2022.10032908","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032908","url":null,"abstract":"Low-power operation and rejection of 50Hz/60Hz power line interference is the prime requirement of notch filter targeted for acquisition of electroencephalogram (EEG) signals. However, achieving low-power operation along with rejection of power line interference using notch filter is difficult task in CMOS technology. In this work, we have proposed a low transconductance quasi-floating bulk (QFB) OTA based 3rd order low-pass notch filter in 0.18 µm standard CMOS process. The proposed 3rd order low-pass notch filter shows passband attenuation of -3.6 dB, stopband attenuation of -13.86 dB, notch of -43.4 dB at 50 Hz, bandwidth of 34.3 Hz and total harmonic distortion (THD) of 1% for input range of 5 mVpp at 8 Hz frequency. The proposed notch filter consumes area of 81990.50 µm2, power of 0.168 µW from ± 0.88 V supply voltage. The proposed notch filter is anticipated to be used in analog front-end systems targeted for detection of biomedical signals such as EEG and electrocardiogram (ECG).","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"232 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121475371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Analytical modeling of Current Spreading Length in Flip chip GaN LEDs 倒装GaN led电流扩展长度的解析建模
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032805
Y. Prasamsha, N. Mohankumar, P. Sriramani
{"title":"Analytical modeling of Current Spreading Length in Flip chip GaN LEDs","authors":"Y. Prasamsha, N. Mohankumar, P. Sriramani","doi":"10.1109/EDKCON56221.2022.10032805","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032805","url":null,"abstract":"In this paper, an Analytical model for the transparent conducting layer is developed for a Flip chip GaN LED. ITO (Indium tin oxide) layer is used as a Current Spreading Layer in the GaN flip chip LEDs and the expressions for the current spreading length are derived. The parameters that affect the CSL are investigated in detail by varying the thickness of the ITO layer. Normally, Flip chip LEDs have more Internal Quantum Efficiency than planar LEDs. The extraction efficiency of the LED can be further improved by taking into account the current spreading length. Numerical analysis and simulations are performed to investigate the advantage of these flip-chip LEDs over conventional planar LEDs.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128266380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of Gaussian Grain Boundary Trap States on the Performance of the LTPS TFTs 高斯晶界阱态对LTPS tft性能的影响
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032858
Saurabh Jaiswal, M. K. Singh, Rupam Gosawmi, M. Goswami, Kavindra Kandpal
{"title":"Impact of Gaussian Grain Boundary Trap States on the Performance of the LTPS TFTs","authors":"Saurabh Jaiswal, M. K. Singh, Rupam Gosawmi, M. Goswami, Kavindra Kandpal","doi":"10.1109/EDKCON56221.2022.10032858","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032858","url":null,"abstract":"This paper presents a study on the impact of grain boundary trap states on the performance of polysilicon thin-film transistors (TFTs. It uses the Synopsys TCAD tool to analyze the device behavior of low-temperature polysilicon (LTPS) TFTs. It has been observed that grain boundary traps in polycrystalline material adversely impact the threshold voltage, subthreshold slope, and mobility. Across the grain boundaries, the primary transport mechanism is thermionic emission and it limits the carrier mobility and carrier concentration. Moreover, it was found that the influence of grain boundary traps was less in TFTs employing high-κ gate dielectrics. With HfO2 gate dielectric the simulated device exhibited the least threshold voltage of 0.85 V, the least subthreshold slope of 80 mV/decade, the highest field-effect mobility of 41 cm2/V-s, and a best on-to-off current ratio of 1.93x108 compared to the TFTs with SiO2 and Si3N4 gate dielectric.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116367867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analytical Modeling of Dielectric Modulated Triple Material Stacked Surrounding Gate Junctionless MOSFET based label free Biosensor 基于无标签MOSFET的介电调制三层材料堆叠周围门无结生物传感器的解析建模
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032806
Indranil Banerjee, S. Bhattacharyya, A. Sarkar
{"title":"Analytical Modeling of Dielectric Modulated Triple Material Stacked Surrounding Gate Junctionless MOSFET based label free Biosensor","authors":"Indranil Banerjee, S. Bhattacharyya, A. Sarkar","doi":"10.1109/EDKCON56221.2022.10032806","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032806","url":null,"abstract":"This article explores and investigates the parametric study of a high-performance 2D Analytical modeling of Dielectric Modulated, Triple Material, Stacked Surrounding Gate Junctionless (DMTMSSGJL) MOSFET based label free biosensor. The biosensing performance parameters namely the surface potential, channel center potential and the threshold voltage has been achieved with the solutions obtained from 2D Poisson’s equation when solved with the aid of cylindrical coordinate system. The dielectric modulation technique has been integrated within the nanogap near the source and drain region to measure the shift in threshold voltage sensitivity for the recognition of various neutral biomolecules such as Biotin, APTES, Gluten, Keratin, and Gelatin. The enhancement in the sensitivity of the model may be achieved by optimizing certain device parameters. These includes oxide thickness (tox), nanogap thickness (tgap), channel length (Lg), nano-gap length (Lgap), alteration of drain voltage (VDS), and work function variation of the metal gate.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125920141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance analysis of PLL based DSGCP (Double Stage Grid Connected Photovoltaic) system with non-linear load under normal and various grid fault conditions 基于锁相环的非线性负载双级并网光伏系统在正常和各种电网故障条件下的性能分析
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032926
Saptaparna Basu Roy Chowdhury, Atanu Maji, P. Gayen, S. Chowdhury
{"title":"Performance analysis of PLL based DSGCP (Double Stage Grid Connected Photovoltaic) system with non-linear load under normal and various grid fault conditions","authors":"Saptaparna Basu Roy Chowdhury, Atanu Maji, P. Gayen, S. Chowdhury","doi":"10.1109/EDKCON56221.2022.10032926","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032926","url":null,"abstract":"The demand for non-conventional energy sources is growing by days and solar energy is one of the leading among these. In order to synchronize Photovoltaic (PV) system with the grid, a few major aspects such as controlling the DC link voltage (Vdc) at the output of DC-DC boost converter and controlling of generation of reference current and pulses for the voltage source inverter (VSI) are to be taken care of. In present work, we have connected a PV plant to the grid by means of DC-DC boost converter and VSI following extraction of maximum power using conventional Perturb & Observe (P&O) method. A non-linear R-L load having total harmonic distortion (THD) of 22.24% has been tied with the same grid and a proportional-integral (PI) controller has been used to control the DC link voltage. Automatic gain control enabled phase locked loop (PLL) is used here for generating gate pulses to the VSI. The entire system has been simulated in Matlab-Simulink environment under normal and different grid fault situations. Harmonics analysis of different system parameters such as inverter current, load current and grid current have been illustrated at pre-fault, during fault and post-fault conditions. It is observed that all the parameters are well within the permissible limit under all situations and capacitor voltage profile also remains almost stable throughout; although, minor and non-similar variations in DC link voltage is noticed during the different grid faults.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127876941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
III-V Heterostucture Transistor with Underlap: A Comparitive Study and Performance Investigation 具有下搭接的III-V异质结构晶体管:比较研究和性能研究
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032956
Prasantakumar Khuntia, Biswajit Baral, S. Biswal, Sudhansu Kumar Pati
{"title":"III-V Heterostucture Transistor with Underlap: A Comparitive Study and Performance Investigation","authors":"Prasantakumar Khuntia, Biswajit Baral, S. Biswal, Sudhansu Kumar Pati","doi":"10.1109/EDKCON56221.2022.10032956","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032956","url":null,"abstract":"MOSFET performs better in high-performance mixed signal applications due to the higher electron mobility caused by the presence of InGaAs in the channel. The numerical TCAD device simulator is used in this study to perform the first Analog/RF analysis of an Inversion-type Enhancement Mode InGaAs Channel.RF performance testing becomes a significant issue in analogue and radio frequency circuit-based applications due to its nonlinearity properties. Recently, heterostructure underlap double gate MOSFETs have shown promise for use in various digital circuits. Devices with underlap architecture perform better as a result of lower coupling capacitance between the contacts (Source-Gate and Gate-Drain). This study verifies a variety of performance indicators, including the transconductance generation factor (TGF), the transconductance (gm), the linearity factor such as 2nd and 3rd order variable intercept and the cut off frequency (fT). There has been a comparison with Junctionless DG MOSFET. The outcomes demonstrate that Heterostucture Underlap DGMOSFET is a powerful competitive device for SOC application with improved RF performance.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127771950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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