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Computation Study of WSe2 Monolayer for Biomarker in Lung Cancer 肺癌生物标志物WSe2单分子层的计算研究
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032891
Prasanna Karki, Bibek Chettri, P. Chettri, S. Das, B. Sharma
{"title":"Computation Study of WSe2 Monolayer for Biomarker in Lung Cancer","authors":"Prasanna Karki, Bibek Chettri, P. Chettri, S. Das, B. Sharma","doi":"10.1109/EDKCON56221.2022.10032891","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032891","url":null,"abstract":"Using Quantum ATK, a computational study of WSe2 as a sensing material is explored using density functional theory (DFT) to investigate properties such as band structure, density of states (DOS), adsorption energy, charge transfer, and recovery time. We propose WSe<inf>2</inf> as a potential biosensor for detecting two commonly exhaled volatile organic compounds (VOCs) in lung cancer, isoprene (C<inf>5</inf>H<inf>8</inf>) and propanal (C<inf>3</inf>H<inf>6</inf>O). For WSe<inf>2</inf>-C<inf>5</inf>H<inf>8</inf>, we measured -0.9 eV adsorption energy and 1.031e charge transfer, and for WSe<inf>2</inf>-C<inf>3</inf>H<inf>6</inf>O, we measured -0.39 eV adsorption energy and 0.004e charge transfer. As a result, the WSe<inf>2</inf>-C<inf>5</inf>H<inf>8</inf> has less adsorption energy and more charge transfer than the WSe<inf>2</inf>-C<inf>3</inf>H<inf>6</inf>O system. Furthermore, the recovery time for C<inf>5</inf>H<inf>8</inf> is 1.07s compared to 4.4 x 10<sup>-7</sup>s for C<inf>3</inf>H<inf>6</inf>O at 348 K.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127351525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Performance Optimization of CdS/CdTe Thin Film Hetrojunction solar cell by SCAPS-1D Simulation 通过 SCAPS-1D 仿真优化 CdS/CdTe 薄膜四元结太阳能电池的性能
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032893
K. Dixit, G. Ahmad
{"title":"Performance Optimization of CdS/CdTe Thin Film Hetrojunction solar cell by SCAPS-1D Simulation","authors":"K. Dixit, G. Ahmad","doi":"10.1109/EDKCON56221.2022.10032893","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032893","url":null,"abstract":"This work presents the study of the structural and physical properties of Cadmium Sulphide and Cadmium Telluride layers on thin-film heterojunction solar cells' performance. The performance evaluation of the solar cell was completed by numerical simulation using the SCAPS-1D open-source solar simulating tool. Herein, we have optimised the PCE of this photovoltaic cell by altering the different parameters of window and absorber layers such as thickness, electron affinity, band gap, and doping concentration using numerical simulation. By varying these parameters, we have done a comparative study to observe the impact on the device performance. Highest electrical conversion efficiency of 19.72% is achieved with numerical simulation when we kept the thickness of CdS and CdTe layers to 0.05 µm and 3 µm respectively.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131412041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Unified Approach for Realization of IIR Filters in Delta Domain 一种统一实现增量域IIR滤波器的方法
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032937
P. Sarkar, A. Mondal, Sujay Kumar Dolai
{"title":"A Unified Approach for Realization of IIR Filters in Delta Domain","authors":"P. Sarkar, A. Mondal, Sujay Kumar Dolai","doi":"10.1109/EDKCON56221.2022.10032937","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032937","url":null,"abstract":"In this paper, digital realization of IIR filters is concentrated in discrete delta domain.Whenever, a continuous time filter is discretised at fast sampling rate, corresponding discrete time filter in conventional z-domain realization fails to provide meaningful information. In other way, the delta domain based system provides the continuous time results at fast sampling rate leading to the development of a unified method for filter realization in digital domain. Realization of the digital filter using delta operator is having very good finite word length performance under high sampling rate. Three different types of IIR filters are considered for the digital realization in delta domain. The transposed delta direct form II (DDFT-II) structure is used to realize the filters, as it is the most suitable structure for digital filter realization. Butterworth, Chebyshev -2 and Elliptic filters are considered as example and Matlab Simulink is used to realize the digital filter in delta domain .The frequency response analysis proves the efficacy of the proposed method.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121161042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effect of deep and tail grain boundary trap states on the performance of poly-ZnO TFT 深晶界和尾晶界阱态对zno TFT性能的影响
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032887
Saurabh Jaiswal, S. Akula, Rupam Gosawmi, M. Goswami, Kavindra Kandpal
{"title":"Effect of deep and tail grain boundary trap states on the performance of poly-ZnO TFT","authors":"Saurabh Jaiswal, S. Akula, Rupam Gosawmi, M. Goswami, Kavindra Kandpal","doi":"10.1109/EDKCON56221.2022.10032887","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032887","url":null,"abstract":"The presence of grain boundaries in polycrystalline ZnO hugely impacts its electrical characteristic. In this work, we have studied the influence of double exponential grain boundary (GB) traps on the performance of a ZnO TFT. It is assumed that all kinds of defects in the ZnO/ gate-dielectric interface and GB are effectively localized in GB traps. Moreover, traps are thermally activated as per the multiple trapping and release (MTR) theory. Using Sentaurus TCAD, the device's behavior has been analyzed and it has been found that the ZnO TFT employing high-κ gate-dielectric exhibits minimal degradation in TFT characteristics in the presence of traps. In the presence of deep state traps, N<inf>deep</inf> =1 ×10<sup>10</sup> cm<sup>−2</sup>eV<sup>−1</sup> and tail state traps N<inf>tail</inf> = 2.85 × 10<sup>13</sup> cm<sup>−2</sup>eV<sup>−1</sup>, TFT with gate-dielectric HfO<inf>2</inf> exhibited least threshold voltage of 0.44 V & a subthreshold slope of 96 mV, and the highest field-effect mobility of 3.6 cm<sup>2</sup>/V − s compared to TFT with SiO<inf>2</inf> and Si<inf>3</inf>N<inf>4</inf> gate-dielectric.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121320570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Study of Plasma Distribution Function in a Paul Trap using Palette Mapped 3D Plots 利用调色板映射三维图研究保罗阱中等离子体分布函数
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032925
Ipshit Ghosh, Varun Saxena, A. Krishnamachari
{"title":"Study of Plasma Distribution Function in a Paul Trap using Palette Mapped 3D Plots","authors":"Ipshit Ghosh, Varun Saxena, A. Krishnamachari","doi":"10.1109/EDKCON56221.2022.10032925","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032925","url":null,"abstract":"The time evolution of a Gaussian plasma distribution function is plotted for a non neutral, collisions less plasma confined in a Paul trap using spatially linear radio frequency (RF) electric field. The distribution function is characterised by a typical fluctuation on account of a slow frequency known as the secular frequency and the RF frequency. Using palette mapped 3D plots we show that the fluctuations are in general a-periodic and there is a phenomena of beat frequency on account of two incommensurate frequencies. However, for a specific set of Paul trap parameters the distribution function becomes independent of the slow frequency and becomes periodic with the period of the applied RF frequency electric field.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129296727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance Analysis of Adiabatic CMOS Interface for Low Power Applications 低功耗绝热CMOS接口的性能分析
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032867
Lalit Rai, Prashant Kumar, N. Gupta, Rashmi Gupta
{"title":"Performance Analysis of Adiabatic CMOS Interface for Low Power Applications","authors":"Lalit Rai, Prashant Kumar, N. Gupta, Rashmi Gupta","doi":"10.1109/EDKCON56221.2022.10032867","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032867","url":null,"abstract":"This paper presents a comparative analysis of Adiabatic and Standard CMOS Interface circuit, for minimizing the power dissipation. The main consideration is to compare the power dissipation of interfaces and optimum results should be obtained. The transient analysis in all the memory cells have been carried out. Furthermore, the variation of power dissipation with temperature and power supply have been investigated. The variation of power delay product with power supply has also been analyzed. The simulations are implemented in 65nm CMOS technology in TSPICE.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"263 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114549045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and Simulation of Double gate Junctionless Field Effect Transistor for Ammonia Gas Sensing 氨气体传感用双栅无结场效应晶体管的设计与仿真
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032918
Divya Babbar, S. Kabra, Yogesh Pratap
{"title":"Design and Simulation of Double gate Junctionless Field Effect Transistor for Ammonia Gas Sensing","authors":"Divya Babbar, S. Kabra, Yogesh Pratap","doi":"10.1109/EDKCON56221.2022.10032918","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032918","url":null,"abstract":"In this work 2-D Junctionless symmetric double gate field effect transistor(DGJL FET) using catalytic metals as gate electrode is designed for ammonia (NH3) gas detection. Two different catalytic metals Cobalt and Molybdenum are used as gate contact because of their selectivity towards NH3 . When the gas molecules of NH3 are adsorbed over the surface of the catalytic metal gate, it causes considerable variation in electrical characteristics of Double gate Junctionless FET.The proposed device has been simulated using 2-D Sentaurus TCAD device Simulation tool. Simulation results of DGJL FET shows that drain current sensitivity(ON & OFF current), threshold voltage and IDON/IDOFF change significantly as the work function of Cobalt and Molybdenum gate changes from 0meV(without gas molecule) to 50meV and upto 200meV. Thus changes in these electrical characteristics have been used to investigate the response of DGJL FET as NH3 gas sensor.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125320705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and Simulation of Ultra-Low-Power Parallel Summation Logarithmic Amplifier 超低功耗并联求和对数放大器的设计与仿真
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032959
Anisha Ahuja, Dr. Usha S. Mehta
{"title":"Design and Simulation of Ultra-Low-Power Parallel Summation Logarithmic Amplifier","authors":"Anisha Ahuja, Dr. Usha S. Mehta","doi":"10.1109/EDKCON56221.2022.10032959","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032959","url":null,"abstract":"This research presents the design and implementation of an ultra-low-power, extended dynamic range CMOS logarithmic amplifier for biomedical applications. Series linear limit Logarithmic amplifiers have a pair of amplifiers, which consumes more area and power. To remove this limitation recommended amplifier is given here using a progressive-compression parallel-summation technique, which uses the cascading of limiting amplifier and DC offset cancellation feedback loop. A DC offset cancellation feedback loop is provided to the design to decrease output saturation and optimize poor input sensitivity caused by associated DC offset voltages. A typical 0.18 µm CMOS technology in the Cadence Virtuoso was used here to design and build the suggested logarithmic amplifier. The complete circuit consumes 14.63 µW total power by using source of 1.5V supply voltage. Gain obtained from the first stage here was 15.95dB. According to observations, the proposed logarithmic amplifier has a 50-dB input dynamic range, the bandwidth of the design is 10 Hz–40 KHz, and the total input referred noise tolerated by the design was 24.128 µV at 10 kHz frequency.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125371728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Unified Surface Potential Based Analytical Modeling of Symmetrical Double Gate AlGaN/GaN MOS-HEMT for Label-Free Bio-Sensing 基于统一表面电位的对称双栅AlGaN/GaN MOS-HEMT无标记生物传感分析建模
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032952
P. Sriramani, N. Mohankumar, Y. Prasamsha
{"title":"Unified Surface Potential Based Analytical Modeling of Symmetrical Double Gate AlGaN/GaN MOS-HEMT for Label-Free Bio-Sensing","authors":"P. Sriramani, N. Mohankumar, Y. Prasamsha","doi":"10.1109/EDKCON56221.2022.10032952","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032952","url":null,"abstract":"This paper presents an analytical surface potential-based drain current model for strong, weak and moderate inversion regions of AlGaN/GaN symmetrical Double gate Metal oxide semiconductor High electron mobility transistor (DG- MOSHEMT). The developed model considers the first and second sub-bands E0, E1 of the quantum well. The impact of drain bias variation on MOS-HEMT for biomedical applications reported for the first time. The developed model is used to analyze the device behavior for scalable physical parameters. Moreover, the developed model is validated by comparing the results with existing experimental data.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126148290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance Comparison and Design of Passive Components for DC-DC Buck-Boost, Cuk and Sepic Converter DC-DC Buck-Boost、Cuk和Sepic变换器无源元件性能比较与设计
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032936
A. Mitra, Sujoy Bhowmik, S. Mukherjee, Pallav Dutta, Kamalika Banerjee, Sudhangshu Sarkar
{"title":"Performance Comparison and Design of Passive Components for DC-DC Buck-Boost, Cuk and Sepic Converter","authors":"A. Mitra, Sujoy Bhowmik, S. Mukherjee, Pallav Dutta, Kamalika Banerjee, Sudhangshu Sarkar","doi":"10.1109/EDKCON56221.2022.10032936","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032936","url":null,"abstract":"With recent development in distributed generation, power demand can be mitigated utilizing DC power and its grid integration. Depending on the grid voltage level, proper selection of DC-DC converter is very essential to optimize the size, compactness and cost of the inverter-transformer assembly. Also, there are so many DC-DC converter topologies among which the step-up/down topologies are very useful to maintain the output voltage level as desired, and also offers a wide range of input resistance. In this proposed work, a comparison between three types of step-up/down converter, i.e., Buck-Boost, Cuk and Sepic converter has been inspected with respect to the sizing of passive components and its cost-effectiveness. The transfer function models are developed through which frequency response and damping ratio of the converters are estimated, so that proper selection of converter along with the passive elements can easily be achieved.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127134134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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