Design and Simulation of Ultra-Low-Power Parallel Summation Logarithmic Amplifier

Abstract

This research presents the design and implementation of an ultra-low-power, extended dynamic range CMOS logarithmic amplifier for biomedical applications. Series linear limit Logarithmic amplifiers have a pair of amplifiers, which consumes more area and power. To remove this limitation recommended amplifier is given here using a progressive-compression parallel-summation technique, which uses the cascading of limiting amplifier and DC offset cancellation feedback loop. A DC offset cancellation feedback loop is provided to the design to decrease output saturation and optimize poor input sensitivity caused by associated DC offset voltages. A typical 0.18 µm CMOS technology in the Cadence Virtuoso was used here to design and build the suggested logarithmic amplifier. The complete circuit consumes 14.63 µW total power by using source of 1.5V supply voltage. Gain obtained from the first stage here was 15.95dB. According to observations, the proposed logarithmic amplifier has a 50-dB input dynamic range, the bandwidth of the design is 10 Hz–40 KHz, and the total input referred noise tolerated by the design was 24.128 µV at 10 kHz frequency.