Effect of deep and tail grain boundary trap states on the performance of poly-ZnO TFT

2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI:10.1109/EDKCON56221.2022.10032887

Saurabh Jaiswal, S. Akula, Rupam Gosawmi, M. Goswami, Kavindra Kandpal

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Abstract

The presence of grain boundaries in polycrystalline ZnO hugely impacts its electrical characteristic. In this work, we have studied the influence of double exponential grain boundary (GB) traps on the performance of a ZnO TFT. It is assumed that all kinds of defects in the ZnO/ gate-dielectric interface and GB are effectively localized in GB traps. Moreover, traps are thermally activated as per the multiple trapping and release (MTR) theory. Using Sentaurus TCAD, the device's behavior has been analyzed and it has been found that the ZnO TFT employing high-κ gate-dielectric exhibits minimal degradation in TFT characteristics in the presence of traps. In the presence of deep state traps, Ndeep =1 ×10¹⁰ cm⁻²eV⁻¹ and tail state traps Ntail = 2.85 × 10¹³ cm⁻²eV⁻¹, TFT with gate-dielectric HfO2 exhibited least threshold voltage of 0.44 V & a subthreshold slope of 96 mV, and the highest field-effect mobility of 3.6 cm²/V − s compared to TFT with SiO2 and Si3N4 gate-dielectric.

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深晶界和尾晶界阱态对zno TFT性能的影响

多晶ZnO中晶界的存在极大地影响了其电学特性。在这项工作中，我们研究了双指数晶界(GB)陷阱对ZnO TFT性能的影响。假设ZnO/栅极介质界面和GB中的各种缺陷都有效地局限于GB陷阱中。此外，根据多重捕获和释放(MTR)理论，圈闭是热激活的。利用Sentaurus TCAD分析了该器件的行为，发现采用高κ栅极介电介质的ZnO TFT在存在陷阱的情况下表现出最小的TFT特性退化。在深态阱Ndeep =1 ×1010 cm−2eV−1和尾态阱Ntail = 2.85 × 1013 cm−2eV−1的情况下，与SiO2和Si3N4栅极介质TFT相比，HfO2栅极介质TFT的阈值电压最小，为0.44 V，亚阈值斜率为96 mV，场效应迁移率最高，为3.6 cm2/V−s。

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2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)

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