Impact of Gaussian Grain Boundary Trap States on the Performance of the LTPS TFTs

This paper presents a study on the impact of grain boundary trap states on the performance of polysilicon thin-film transistors (TFTs. It uses the Synopsys TCAD tool to analyze the device behavior of low-temperature polysilicon (LTPS) TFTs. It has been observed that grain boundary traps in polycrystalline material adversely impact the threshold voltage, subthreshold slope, and mobility. Across the grain boundaries, the primary transport mechanism is thermionic emission and it limits the carrier mobility and carrier concentration. Moreover, it was found that the influence of grain boundary traps was less in TFTs employing high-κ gate dielectrics. With HfO2 gate dielectric the simulated device exhibited the least threshold voltage of 0.85 V, the least subthreshold slope of 80 mV/decade, the highest field-effect mobility of 41 cm2/V-s, and a best on-to-off current ratio of 1.93x108 compared to the TFTs with SiO2 and Si3N4 gate dielectric.