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2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)最新文献

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Area Efficient Energy Saving Inexact Multiplier for Error Resilient Applications 面向纠错应用的面积高效节能非精确乘法器
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032922
Tharun Kumar Guduru, Papanasam Esakki, M. E, Manikandan Nagarajan
{"title":"Area Efficient Energy Saving Inexact Multiplier for Error Resilient Applications","authors":"Tharun Kumar Guduru, Papanasam Esakki, M. E, Manikandan Nagarajan","doi":"10.1109/EDKCON56221.2022.10032922","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032922","url":null,"abstract":"In this paper, we proposed energy efficient-compact approximate multiplier using the compressor technique with a full adder, half adder, and OR gate. A full adder in the least significant digit (LSD) of the exact compressor is replaced by a half adder and OR gate. The proposed compressor exhibits better performance with 23.3% less power, 20% reduction in area, and 4.1% less delay than an exact compressor. The error rate of the proposed compressor is as small as 6.5 %. 8-bit and 16-bit multipliers are designed using the proposed OR compressor and the performance metrics of proposed multipliers are compared with both the exact and existing approximate multipliers. The 8-bit multiplier implemented using the proposed compressor improves the speed by 50.4%, reduces the power by 34.1%, and saves the area by 58.9% with an acceptable error rate of 29.5 %. Further, the 16-bit hybrid multiplier designed using the proposed compressor reduces both PDP value and area by 6.4 % and 41.7 % respectively.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129868399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A super Threshold Compact Silicon Neuron Circuit for Different Neuron Dynamics Suitable for Spiking Neural Network 一种适用于脉冲神经网络的超阈值紧凑硅神经元电路
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032919
Sayantan Samanta, Koushik Naskar, Souvanik Pal, Suman Mallik, Sudipta Ghosh, Swarnil Roy
{"title":"A super Threshold Compact Silicon Neuron Circuit for Different Neuron Dynamics Suitable for Spiking Neural Network","authors":"Sayantan Samanta, Koushik Naskar, Souvanik Pal, Suman Mallik, Sudipta Ghosh, Swarnil Roy","doi":"10.1109/EDKCON56221.2022.10032919","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032919","url":null,"abstract":"In this work we have designed and simulated a compact accelerated time silicon neuron circuit in super threshold to achieve proper neural dynamics. With this circuit we have accurately modeled regular spiking (RS), fast spiking (FS), chattering (CH) and intrinsic bursting (IB). The functionality of this circuit is verified with extreme simulation in 32nm, 45nm and 22nm FinFET technology. For this circuits we have analyzed different comparator circuits to meet the required dynamics and concluded that threshold modified comparator serves our purpose best.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128530699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Scheme for Torque Ripple Minimization in BLDC Drive Using Two-Inductor Boost Converter 基于双电感升压变换器的无刷直流驱动转矩脉动最小化方案
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032907
S. Saha, Santanu Modal, M. Chattopadhyay, Moumita Mukherjee
{"title":"A Scheme for Torque Ripple Minimization in BLDC Drive Using Two-Inductor Boost Converter","authors":"S. Saha, Santanu Modal, M. Chattopadhyay, Moumita Mukherjee","doi":"10.1109/EDKCON56221.2022.10032907","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032907","url":null,"abstract":"This paper presents a two-inductor boost converter fed brushless DC (BLDC) motor drive. In this work, a two-inductor boost converter is implemented with the BLDC motor drive for torque ripple reduction. The presence of torque ripple prevents application of BLDC motor drive in high precision works. The two-inductor boost converter used here provides very high gain at comparatively much lower duty ratio, thus eliminating the requirement of higher duty ratio for higher voltage gain. The proposed topology of the BLDC drive has been implemented using MATLAB Simulink. The Fast Fourier Transform (FFT) analysis has been performed on the proposed BLDC motor drive. Also, a comparative analysis of the proposed drive has been presented with SEPIC converter-based BLDC motor drive.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131968688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Study on Sensitivity Parameters of Staggered Heterojunction Gate Stack Tunnel FET Biosensor 交错异质结栅堆隧道场效应晶体管生物传感器灵敏度参数研究
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032909
Kishore Chandra Singh, S. Biswal, Biswajit Baral, S. K. Das, Prasantakumar Khuntia
{"title":"Study on Sensitivity Parameters of Staggered Heterojunction Gate Stack Tunnel FET Biosensor","authors":"Kishore Chandra Singh, S. Biswal, Biswajit Baral, S. K. Das, Prasantakumar Khuntia","doi":"10.1109/EDKCON56221.2022.10032909","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032909","url":null,"abstract":"In this study, we suggest a label-free, low-power biosensor based on a staggered heterojunction gate stack tunnel field-effect transistor (SHGS TFET). A SHGS TFET-based biosensor has not yet been experimentally developed, although a FET-based biosensor with a nanogap cavity already devloped. As a result, an analytical and simulation-based study presents an idea for a SHGS TFET-based sensor. Comparing with conventional TFET-based biosensor, the results show improved responsiveness to two different properties (dielectric constant and charge of biomolecules). TFET is a desirable different design for CMOS-built sensor uses due to its compatibility with CMOS, low leakage, sharp subthreshold slope, and other benefits. Even while FET-based biosensors have many benefits, their short channel effects (SCEs) and theoretically-restricted subthreshold swing (SS > 60 mv/dec) limit the device’s sensitivity and increase power dissipation because of thermionic electron emission. Researchers concentrate on SHGS TFET-based biosensors, which have superior features and low power consumption because of band-to-band carrier tunnelling and steep subthreshold swing. The device performances like the analog as well as sensitivity characteristics is evaluated by taking into consideration biomolecules like protein (K=2.5), aptes (K=3.56), as biomolecules in the cavity and using silicon as the channel material. For simulating persistence the 2D Sentaraus TCAD simulator has been used. In-depth information about Staggered Heterojunction Gate Stack Tunnel FET based biosensors is covered in this report. This information includes qualitative and quantitative parameter analysis studies like sensitivity parameters and various factors affecting sensitivity by comparing various structures and the mechanisms at play. The report also includes a synopsis of several sensitivity criteria.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130813300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.3 V, 4th order low-pass OTA-C filter using bulk-driven technique for EEG applications 一个0.3 V, 4阶低通OTA-C滤波器，采用批量驱动技术，用于脑电图应用
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032944
Diksha Thakur, K. Sharma, Rajnish Sharma
{"title":"A 0.3 V, 4th order low-pass OTA-C filter using bulk-driven technique for EEG applications","authors":"Diksha Thakur, K. Sharma, Rajnish Sharma","doi":"10.1109/EDKCON56221.2022.10032944","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032944","url":null,"abstract":"Low-pass-filter (LPF) is one of the most important building blocks for the effective implementation of any wearable/non-invasive biological system. This manuscript, presents an ultra-low-power, low-voltage bulk-driven (BD) 4th order LPF circuit targeted for the detection of Electroencephalography (EEG) signal. The proposed LPF circuit works in the sub-threshold region to achieve low-power and low-noise operation. The simulated results obtained for proposed LPF CMOS in 180 nm technology node demonstrates -0.10 dB of dc-gain, 52.71 dB of dynamic range of (DR), 92 µVrms of input-referred noise (IRN) and 100 Hz of bandwidth. The LPF consumes power of 0.81 nW at 0.3 V of low-supply voltage. Using the most reasonable and relevant figure of merit (FOM), the proposed LPF circuit outperforms other modern nano-power LPF circuits and is most suitable for EEG acquisition systems.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130250380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Comparative Analysis of Short Channel Effects in Dopingless Charge Plasma Based Nanowire FET 无掺杂电荷等离子体纳米线场效应管短通道效应的比较分析
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032885
Ratul Kundu, Sheikh Mohd. Ta-Seen Afrid, Fahim Abid Rahee, Q.D. Mohd Khosru
{"title":"Comparative Analysis of Short Channel Effects in Dopingless Charge Plasma Based Nanowire FET","authors":"Ratul Kundu, Sheikh Mohd. Ta-Seen Afrid, Fahim Abid Rahee, Q.D. Mohd Khosru","doi":"10.1109/EDKCON56221.2022.10032885","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032885","url":null,"abstract":"Doing less gate all around (GAA) charge plasma (CP) based field effect transistor (FET) has exhibited better performance in terms of short channel effects (SCE) compared to junction-less (JL) FET. GaN has displayed promising characteristics towards bringing down SCEs in charge plasma-based devices for having higher electron mobility and wide band gap properties. In this work, four different wide band gap materials such as GaAs, Al0.1Ga0.9As, InP, and GaN were utilized in the intrinsic channel of charge plasma-based doping less FET to compare the transfer characteristics and transconductance (gm). SCEs such as drain-induced barrier lowering (DIBL) and subthreshold slope (SS) were compared and the figure of merit (FOM), Q (gm/SS) was also calculated. Subsequently, high–k dielectric material’s effect on Ion, Ioff, and Ion/Ioff at gate oxide were investigated for low power applications. Our findings revealed that CP–GaAs showed a better tradeoff between DIBL and SS in comparison to CP–GaN. Also, CP–InP produced a higher threshold device that can be used in the field of memory design. In contrast with Q factor, CP–GaN produced a higher value but CP–GaAs showed a better DIBL–SS value. Hence, both CP–GaN and CP–GaAs can be considered for high-switching applications. Also, CP–GaN produced higher transconductance than other channel materials which will offer the new scheme to enhance device performance.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"420 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116229391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Simulation Study of Hybrid Carrier Selective Passivating Contacts for n-Silicon Solar Cells n-硅太阳电池杂化载流子选择性钝化触点的模拟研究
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032864
Bisma Bilal, Hakim Najeeb-ud-din
{"title":"A Simulation Study of Hybrid Carrier Selective Passivating Contacts for n-Silicon Solar Cells","authors":"Bisma Bilal, Hakim Najeeb-ud-din","doi":"10.1109/EDKCON56221.2022.10032864","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032864","url":null,"abstract":"The performance investigation of silicon heterojunction solar cells is gaining considerable attention with the development of various contact schemes. Carrier selective contacts such as Tunnel Oxide Passivated Contact (TOPCon) and transition metal oxide (TMO) designs are particularly of interest due to excellent passivation, conductivity and selectivity they provide to the two types of carriers. In this paper, the performance of an n-silicon heterojunction solar cell using TOPCon and TMO contacts is investigated. The figures of merit for the proposed cell are extracted at the outset. Further optical analysis, effect of parameters like absorber thickness and interface passivation are discussed. The reported results emphasize on the merits of front wide band-gap TMO and use of passivation layers for improving the performance of the solar cell using hybrid carrier selective passivating contacts.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121616937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of Gate engineering on Analog, RF Performance of Nanoscale Barriered TM-Heterostructure DG-MOSFET 栅极工程对纳米阻挡tm -异质结构DG-MOSFET模拟、射频性能的影响
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032938
Pradipta Kumar Jena, Prasantakumar Khuntia, Biswajit Baral, Sudhansu Kumar Pati
{"title":"Impact of Gate engineering on Analog, RF Performance of Nanoscale Barriered TM-Heterostructure DG-MOSFET","authors":"Pradipta Kumar Jena, Prasantakumar Khuntia, Biswajit Baral, Sudhansu Kumar Pati","doi":"10.1109/EDKCON56221.2022.10032938","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032938","url":null,"abstract":"In this paper, the authors have analyzed Analog, RF and Linearity performance of barriered TM-Heterostructure DG-MOSFET using TCAD device simulation. The model analyzes the effect of gate structure made up of triple material on the electrical performance of the device for variation in potential and Electric Field. The effect of gate engineering on the various Analog and RF performance of a TM-Heterostructure DG MOSFET is thoroughly investigated. For several triple material gates with the ratios 1:1:1, 1:2:3, and 3:2:1, a complete analysis of figures of merit such as transconductance (gm), output resistance (Ro), cut-off frequency (fT), and maximum frequency of oscillation (fmax) is conducted.. We observed from the comparative study that performance of nanoscale TM-DG heterostructure MOSFET gets affected by varying gate length ratio of the device.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133094698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low Power CMOS Comparator with low offset voltage and good resolution for 10-bit SAR ADC 低功耗CMOS比较器，具有低偏置电压和良好的分辨率，用于10位SAR ADC
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032889
K. Mazumdar, Kunjan Amiya Shah, A. Ghosal
{"title":"Low Power CMOS Comparator with low offset voltage and good resolution for 10-bit SAR ADC","authors":"K. Mazumdar, Kunjan Amiya Shah, A. Ghosal","doi":"10.1109/EDKCON56221.2022.10032889","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032889","url":null,"abstract":"In this research paper, a CMOS comparator has been designed using 180 nm technology node. The purpose of this design is to minimize the power consumption and reduce the offset voltage of the comparator block. An Analog to Digital Converter (ADC) designed with this designed comparator will be compatible with low-power applications and provide good resolution. The proposed comparator can also be used for detectors requiring high sensitivity.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"198 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134121798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Computation of In-Plane and Characteristic Impedance of Microstrip Structure under Plasmonic Resonance 等离子体共振下微带结构面内阻抗和特性阻抗的计算
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032900
P. Debnath, Ujjwal Mondal, A. Deyasi
{"title":"Computation of In-Plane and Characteristic Impedance of Microstrip Structure under Plasmonic Resonance","authors":"P. Debnath, Ujjwal Mondal, A. Deyasi","doi":"10.1109/EDKCON56221.2022.10032900","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032900","url":null,"abstract":"In-plane impedance and characteristic impedance of planar microstrip structure is analytically computed for the surface oscillation of electrons owing to formation of surface plasmon polariton. Dimensional parametric ranges are kept in millimeter range for practical design and impedance is computed upto X band from the knowledge of propagation vector variation. Both Faraday inductance and kinetic inductance are separately computed for calculating in-plane impedance, where skin depth for that particular material of the stripline is considered. Realistic materials with standard range of electron density are considered for simulation work. Very low magnitude of characteristic impedance and moderate value of im-plane impedance together reveal sustainable plasmonic resonance for the microstrip structure along the plane of propagation.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133380127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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