Area Efficient Energy Saving Inexact Multiplier for Error Resilient Applications

Abstract

In this paper, we proposed energy efficient-compact approximate multiplier using the compressor technique with a full adder, half adder, and OR gate. A full adder in the least significant digit (LSD) of the exact compressor is replaced by a half adder and OR gate. The proposed compressor exhibits better performance with 23.3% less power, 20% reduction in area, and 4.1% less delay than an exact compressor. The error rate of the proposed compressor is as small as 6.5 %. 8-bit and 16-bit multipliers are designed using the proposed OR compressor and the performance metrics of proposed multipliers are compared with both the exact and existing approximate multipliers. The 8-bit multiplier implemented using the proposed compressor improves the speed by 50.4%, reduces the power by 34.1%, and saves the area by 58.9% with an acceptable error rate of 29.5 %. Further, the 16-bit hybrid multiplier designed using the proposed compressor reduces both PDP value and area by 6.4 % and 41.7 % respectively.