Diminished Short Channel Effects (SCEs) in Junction Less Double Gate (JL DG) MOSFET

Abstract

An analysis of Junction less DG MOSFET structure using TCAD is presented in this paper. The effect of variation in silicon thickness has been investigated for the JL DG MOSFET. The transconductance of proposed structure has been evaluated for the variation in dielectric constant and oxide thickness. The key metric parameters are evaluated for the JL DG MOSFET. Furthermore, parameters are compared with JL SG MOSFET. The proposed device structure shows an excellent immunity against SCEs. The silicon substrate has been replaced with germanium substrate in JL DG MOSFET and comparison has been carried out. The germanium transistors show a reduction in DIBL.