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Proceedings of the 30th European Solid-State Circuits Conference最新文献

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1-58 Gb/s PRBS generator with <1.1 ps RMS jitter in InP technology InP技术中RMS抖动<1.1 ps的1-58 Gb/s PRBS发生器
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356692
H. Veenstra
{"title":"1-58 Gb/s PRBS generator with <1.1 ps RMS jitter in InP technology","authors":"H. Veenstra","doi":"10.1109/ESSCIR.2004.1356692","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356692","url":null,"abstract":"Pseudo-random binary sequence (PRBS) generators are widely used for testing communication systems. This paper describes a fully integrated PRBS generator, supporting output data rates between 1-58 Gb/s, with output jitter below 1.1 ps RMS, requiring only a single reference clock input. This has been achieved, based on impedance-matched clock signal distribution and transmission line modelling. Two half-rate outputs from the PRBS generator core are multiplexed to form the high-speed data output. The IC provides a trigger signal output plus all-zero detection and correction functionality.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116754386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A 14-V high speed driver in 5-V-only 0.35-/spl mu/m standard CMOS 一个14v高速驱动器在5v仅0.35-/spl mu/m标准CMOS
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356640
D. Killat, O. Salzmann, A. Baumgaertner
{"title":"A 14-V high speed driver in 5-V-only 0.35-/spl mu/m standard CMOS","authors":"D. Killat, O. Salzmann, A. Baumgaertner","doi":"10.1109/ESSCIR.2004.1356640","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356640","url":null,"abstract":"A high-voltage and high-speed driver, using only 5-V and 3.3-V technology features in 0.35-/spl mu/m standard CMOS, is presented. The pull-up function is performed by cascaded 5-V PMOS; a 5-V CMOS compatible gate-shifted LDD NMOS performs the pull-down. The maximum continuous operating voltage is 14 V. The driver is suitable for inductive and capacitive loads. An external MOSFET with 1 nF gate capacitance is fully switched in 200 ns, the peak current that the driver delivers is more than 100 mA. The area of the driver including pad is 0.18 mm/sup 2/. The paper discusses characteristics and lifetime of the driver transistors, design trade-offs, and presents simulations, measurement results and statistical data.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115112547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A digital CMOS micro-hotplate array for analysis of environmentally relevant gases 用于分析环境相关气体的数字CMOS微热板阵列
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356677
U. Frey, M. Graf, S. Taschini, K. Kirstein, C. Hagleitner, A. Hierlemann, H. Baltes
{"title":"A digital CMOS micro-hotplate array for analysis of environmentally relevant gases","authors":"U. Frey, M. Graf, S. Taschini, K. Kirstein, C. Hagleitner, A. Hierlemann, H. Baltes","doi":"10.1109/ESSCIR.2004.1356677","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356677","url":null,"abstract":"A monolithic gas sensor array fabricated in industrial CMOS-technology combined with post-CMOS micromachining is presented. The device comprises an array of three metal-oxide-coated micro-hotplates with integrated MOS-transistor heaters and the needed driving and signal-conditioning circuitry. The operating temperature of the SnO/sub 2/ metal oxide resistors varies between 200 and 350/spl deg/C. Three digital PID controllers enable individual temperature regulation. Interface and temperature control are implemented digitally, making a power-saving mode and temperature modulation, to enhance the analyte discrimination, applicable. Emphasis was placed on a modular system with the required analog circuitry reduced to a minimum.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"12 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125426604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 2.7mW 1MSps 10b analog-to-digital converter with built-in reference buffer and 1LSB accuracy programmable input ranges 内置参考缓冲器和1LSB精度可编程输入范围的2.7mW 1MSps 10b模数转换器
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356666
P. Confalonieri, M. Zamprogno, Francesca Girardi, G. Nicollini, A. Nagari
{"title":"A 2.7mW 1MSps 10b analog-to-digital converter with built-in reference buffer and 1LSB accuracy programmable input ranges","authors":"P. Confalonieri, M. Zamprogno, Francesca Girardi, G. Nicollini, A. Nagari","doi":"10.1109/ESSCIR.2004.1356666","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356666","url":null,"abstract":"A CMOS 1 MSps 10 bit charge-redistribution SAR ADC processes single-ended signals with 1 LSB accuracy selectable input ranges up to supply voltage. A new DAC architecture presents the benefits of a differential approach while sampling single-ended signals. Thanks to new low power design solutions in the ADC comparator and the built-in reference buffer, the total ADC power consumption is only 2.7 mW at 2.4 V supply and 1 MSps. The active area is 0.4 mm/sup 2/ in a 0.35 /spl mu/m CMOS process.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126179445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
VLSI implementation of the sphere decoding algorithm VLSI实现球体解码算法
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356678
A. Burg, M. Wenk, Martin Zellweger, M. Wegmueller, N. Felber, W. Fichtner
{"title":"VLSI implementation of the sphere decoding algorithm","authors":"A. Burg, M. Wenk, Martin Zellweger, M. Wegmueller, N. Felber, W. Fichtner","doi":"10.1109/ESSCIR.2004.1356678","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356678","url":null,"abstract":"Maximum likelihood detection is an essential part of high-performance multiple-input-multiple-output (MIMO) communication systems. While it is attractive due to its superior performance (in terms of BER) its complexity using a straightforward exhaustive search grows exponentially with the number of antennas and the order of the modulation scheme. Sphere decoding is a promising method to reduce the average decoding complexity significantly without compromising performance. This paper discusses the VLSI implementation of the sphere decoder and presents the first implementation of the algorithm that does not compromise BER performance.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129772163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
A wideband high-linearity RF receiver front-end in CMOS 一种基于CMOS的宽带高线性射频接收机前端
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356620
V. Arkesteijn, E. Klumperink, B. Nauta
{"title":"A wideband high-linearity RF receiver front-end in CMOS","authors":"V. Arkesteijn, E. Klumperink, B. Nauta","doi":"10.1109/ESSCIR.2004.1356620","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356620","url":null,"abstract":"This paper presents a wideband high-linearity RF receiver-front-end, implemented in standard 0.18 /spl mu/m CMOS technology. The design employs a noise-canceling LNA in combination with two passive mixers, followed by lowpass-filtering and amplification at IF. The achieved bandwidth is >2 GHz, with a noise figure of 6.5 dB, +1 dBm IIP/sub 3/, +34.5 dBm IIP/sub 2/ and <50 kHz 1/f-noise corner frequency.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131131000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A physically oriented model to quantify the dynamic noise margin [on-chip noise] 以物理为导向的模型来量化动态噪声裕度[片内噪声]
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356719
T. Gemmeke, T. Noll
{"title":"A physically oriented model to quantify the dynamic noise margin [on-chip noise]","authors":"T. Gemmeke, T. Noll","doi":"10.1109/ESSCIR.2004.1356719","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356719","url":null,"abstract":"The increase in on-chip noise has led to severe signal integrity problems in modern chip design. In a new approach, an analytical, physically motivated model is proposed which quantities the pulse transfer characteristic of a gate, aimed at quick circuit analysis. The accuracy of the model is validated in comparison with simulation results from a circuit simulator. Moreover, its application in a standard design flow is demonstrated. As the model is based on physical circuit parameters, it is also well suited for what-if analysis.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115833503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A power cut-off technique for gate leakage suppression [CMOS logic circuits] 一种抑制栅漏的电源切断技术[CMOS逻辑电路]
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356645
Mindaugas Draidiiulis, P. Larsson-Edefors, D. Eckerbert, H. Eriksson
{"title":"A power cut-off technique for gate leakage suppression [CMOS logic circuits]","authors":"Mindaugas Draidiiulis, P. Larsson-Edefors, D. Eckerbert, H. Eriksson","doi":"10.1109/ESSCIR.2004.1356645","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356645","url":null,"abstract":"Gate leakage power dissipation is predicted to overtake subthreshold leakage power within the next few years thus adding further problems for designers trying to meet a strict power budget. In this paper, a power cut-off technique is proposed, which in sleep mode suppresses not only subthreshold leakage but also gate leakage. The proposed technique displays a combination of low total leakage power and short wake-up time.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121190447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A technique to reduce flicker noise up-conversion in CMOS LC voltage-controlled oscillators 一种降低CMOS LC压控振荡器闪烁噪声的上变频技术
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356633
H. Shanan, Michael Peter Kennedy
{"title":"A technique to reduce flicker noise up-conversion in CMOS LC voltage-controlled oscillators","authors":"H. Shanan, Michael Peter Kennedy","doi":"10.1109/ESSCIR.2004.1356633","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356633","url":null,"abstract":"This work presents a technique for reducing the flicker noise up-conversion to phase noise in CMOS LC voltage-controlled oscillators (VCOs). The technique is a modification to a standard VCO, which can achieve about 6 dB of improvement in phase noise at close frequency offsets to the radio frequency (RF) carrier. The same technique has been applied to a differential Colpitts oscillator and achieved the same level of improvement compared to a standard VCO. A reference VCO, a modified VCO and a differential Colpitts VCO were designed to have the same bias current, the same fundamental frequency, the same frequency tuning range, the same gain, the same inductor value and the same output voltage swing to allow for a fair comparison between the oscillator architectures. The VCOs were fabricated using the CMOS part of a 0.35 /spl mu/m BiCMOS process. Measurement results validate the simulations.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127794039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A cavity channel SESO embedded memory with low standby-power techniques 一种具有低待机功耗技术的腔通道SESO嵌入式存储器
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356690
B. Atwood, T. Ishii, Takao Watanabe, T. Mine, N. Kameshiro, T. Sano, K. Yano
{"title":"A cavity channel SESO embedded memory with low standby-power techniques","authors":"B. Atwood, T. Ishii, Takao Watanabe, T. Mine, N. Kameshiro, T. Sano, K. Yano","doi":"10.1109/ESSCIR.2004.1356690","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356690","url":null,"abstract":"A 22F/sup 2/ 3-transistor dynamic memory cell, based on a newly fabricated cavity channel SESO (single-electron shutoff) transistor is proposed for low-power mobile SOCs. The ultra-low leakage SESO device is formed above the bulk devices to yield the small cell size. With low-power techniques, this memory can achieve nearly an order of magnitude lower standby power than conventional memory. A 1 Mbyte SESO embedded memory core is estimated to have a standby power consumption of 24.2 /spl mu/A in a 90 nm process.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130740535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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