P. Confalonieri, M. Zamprogno, Francesca Girardi, G. Nicollini, A. Nagari
{"title":"内置参考缓冲器和1LSB精度可编程输入范围的2.7mW 1MSps 10b模数转换器","authors":"P. Confalonieri, M. Zamprogno, Francesca Girardi, G. Nicollini, A. Nagari","doi":"10.1109/ESSCIR.2004.1356666","DOIUrl":null,"url":null,"abstract":"A CMOS 1 MSps 10 bit charge-redistribution SAR ADC processes single-ended signals with 1 LSB accuracy selectable input ranges up to supply voltage. A new DAC architecture presents the benefits of a differential approach while sampling single-ended signals. Thanks to new low power design solutions in the ADC comparator and the built-in reference buffer, the total ADC power consumption is only 2.7 mW at 2.4 V supply and 1 MSps. The active area is 0.4 mm/sup 2/ in a 0.35 /spl mu/m CMOS process.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"34","resultStr":"{\"title\":\"A 2.7mW 1MSps 10b analog-to-digital converter with built-in reference buffer and 1LSB accuracy programmable input ranges\",\"authors\":\"P. Confalonieri, M. Zamprogno, Francesca Girardi, G. Nicollini, A. Nagari\",\"doi\":\"10.1109/ESSCIR.2004.1356666\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A CMOS 1 MSps 10 bit charge-redistribution SAR ADC processes single-ended signals with 1 LSB accuracy selectable input ranges up to supply voltage. A new DAC architecture presents the benefits of a differential approach while sampling single-ended signals. Thanks to new low power design solutions in the ADC comparator and the built-in reference buffer, the total ADC power consumption is only 2.7 mW at 2.4 V supply and 1 MSps. The active area is 0.4 mm/sup 2/ in a 0.35 /spl mu/m CMOS process.\",\"PeriodicalId\":294077,\"journal\":{\"name\":\"Proceedings of the 30th European Solid-State Circuits Conference\",\"volume\":\"44 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-11-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"34\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 30th European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIR.2004.1356666\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 30th European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIR.2004.1356666","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 2.7mW 1MSps 10b analog-to-digital converter with built-in reference buffer and 1LSB accuracy programmable input ranges
A CMOS 1 MSps 10 bit charge-redistribution SAR ADC processes single-ended signals with 1 LSB accuracy selectable input ranges up to supply voltage. A new DAC architecture presents the benefits of a differential approach while sampling single-ended signals. Thanks to new low power design solutions in the ADC comparator and the built-in reference buffer, the total ADC power consumption is only 2.7 mW at 2.4 V supply and 1 MSps. The active area is 0.4 mm/sup 2/ in a 0.35 /spl mu/m CMOS process.
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