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Proceedings of the 30th European Solid-State Circuits Conference最新文献

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Towards an AES crypto-chip resistant to differential power analysis 一种抗差分功率分析的AES加密芯片
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356679
Norbert Pramstaller, Frank K. Gürkaynak, S. Haene, H. Kaeslin, N. Felber, W. Fichtner
{"title":"Towards an AES crypto-chip resistant to differential power analysis","authors":"Norbert Pramstaller, Frank K. Gürkaynak, S. Haene, H. Kaeslin, N. Felber, W. Fichtner","doi":"10.1109/ESSCIR.2004.1356679","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356679","url":null,"abstract":"Differential power analysis (DPA) implies measuring the supply current of a cipher-circuit in an attempt to uncover part of a cipher-key. Cryptographic security gets compromised if the current waveforms so obtained correlate with those from a hypothetical power model of the circuit. Such correlations can be minimized by masking datapath operations with random bits in a reversible way. We analyze such countermeasures and discuss how they perform and how well they lend themselves to being incorporated into dedicated hardware implementations of the advanced encryption standard (AES) block cipher. Our favorite masking scheme entails a performance penalty of some 40-50%. We also present a VLSI design that can serve for practical experiments with DPA.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131607547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 50
Fully integrated ultra wide band CMOS low noise amplifier 全集成超宽带CMOS低噪声放大器
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356711
C. Grewing, M. Friedrich, G. Puma, C. Sandner, S. Waasen, A. Wiesbauer, K. Winterberg
{"title":"Fully integrated ultra wide band CMOS low noise amplifier","authors":"C. Grewing, M. Friedrich, G. Puma, C. Sandner, S. Waasen, A. Wiesbauer, K. Winterberg","doi":"10.1109/ESSCIR.2004.1356711","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356711","url":null,"abstract":"A single ended low noise amplifier (LNA) in distributed amplifier technique for ultra wide band (UWB) fabricated in a standard 0.13 /spl mu/m CMOS technology is presented. Measurement results are given for a chip-on-board module to take possible influences of a product assembly into account. The amplifier provides 15 dB gain with a corner frequency up to 5 GHz, a noise figure of 4.5 dB to 5.5 dB at 50 /spl Omega/ in this frequency range and an input 1 dB-compression point of -5 dBm.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116164270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 14-bit 130-MHz CMOS current-steering DAC with adjustable INL 具有可调INL的14位130 mhz CMOS电流转向DAC
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356644
Tao Chen, P. Geens, G. V. D. Plas, W. Dehaene, G. Gielen
{"title":"A 14-bit 130-MHz CMOS current-steering DAC with adjustable INL","authors":"Tao Chen, P. Geens, G. V. D. Plas, W. Dehaene, G. Gielen","doi":"10.1109/ESSCIR.2004.1356644","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356644","url":null,"abstract":"In this paper, a 14-bit, 130-MHz CMOS current-steering DAC is presented. Different from traditional intrinsic-accuracy DACs, its INL can be improved by dynamic adjustment, which allows a significant reduction of the chip area. The layout has been carefully designed so that the signal lines of the current sources have the same length, thus good synchronization among the current sources can be achieved. The measured DNL and INL is 0.45 LSB and 0.7 LSB respectively. The spurious-free dynamic range is 82 dB at a 1 MHz signal frequency and 130 MHz sampling frequency. The DAC has been implemented in a standard 1P5M 0.25-/spl mu/m CMOS technology. The area of the current source block is 1 mm/sup 2/, and the whole core area is only 3.5 mm/sup 2/.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122287612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Silicon bipolar up and down-converters for 5-GHz WLAN applications 用于5 ghz WLAN应用的硅双极上下转换器
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356621
E. Ragonese, A. Italia, L. Paglia, G. Palmisano
{"title":"Silicon bipolar up and down-converters for 5-GHz WLAN applications","authors":"E. Ragonese, A. Italia, L. Paglia, G. Palmisano","doi":"10.1109/ESSCIR.2004.1356621","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356621","url":null,"abstract":"A dB-linear variable-gain up-converter and an image-reject down-converter for 5-GHz wireless LAN applications were implemented in a 46-GHz-f/sub T/ silicon bipolar technology. The up-converter exhibits a 13-dB power gain and an output 1-dB compression point of 6 dBm. It adopts a digital pre-distortion technique to achieve a linear-in-dB gain characteristic with a dynamic range of 30 dB. The down-converter exhibits a 4-dB noise figure and a power gain of 23 dB. By using a 1-bit gain control it also achieves an input 1-dB compression point of -14 dBm. An image-rejection approach based on monolithic passive notch filters provides an image rejection ratio higher than 60 dB.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122209069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
55GHz CMOS frequency divider with 3.2GHz locking range 55GHz CMOS分频器，3.2GHz锁定范围
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356636
Ken Yamamoto, M. Fujishima
{"title":"55GHz CMOS frequency divider with 3.2GHz locking range","authors":"Ken Yamamoto, M. Fujishima","doi":"10.1109/ESSCIR.2004.1356636","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356636","url":null,"abstract":"LC-resonator frequency dividers are used for high-speed operation. In particular a differential injection locking frequency divider is promising as a millimeter-wave-band divider However, its locking range is narrow and insufficient for practical use. In this paper, several layout techniques are described to improve the performance of the frequency divider, and the performance improvement is verified using a five-layer-metal and 0.2-/spl mu/m-gate CMOS process. Measurement results reveal the minimum and maximum operating frequencies to be 52.7 GHz and 55.9 GHz with 10.1 mW at a supply voltage of 1.0 V.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124109565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 59
The impact of random doping effects on CMOS SRAM cell 随机掺杂效应对CMOS SRAM电池的影响
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356657
B. Cheng, S. Roy, A. Asenov
{"title":"The impact of random doping effects on CMOS SRAM cell","authors":"B. Cheng, S. Roy, A. Asenov","doi":"10.1109/ESSCIR.2004.1356657","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356657","url":null,"abstract":"The SRAM has a very constrained cell area and is consequently sensitive to the intrinsic parameter fluctuations ubiquitous in decananometer scale MOSFETs. Using a statistical circuit simulation methodology, which can fully collate intrinsic parameter fluctuation information into compact model sets, the impact of random device doping on 6-T SRAM static noise margins, and read and write characteristics are investigated in detail for well-scaled 35 nm physical gate length devices. We conclude that intrinsic parameter fluctuations will become a major limitation to further conventional MOSFET SRAM scaling.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117007360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 98
5 Gbps 0.35-/spl mu/m CMOS driver for laser diode or optical modulator 用于激光二极管或光调制器的5gbps 0.35-/spl mu/m CMOS驱动器
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356672
Lianming Li, Ting Huang, Jun Feng, Zhigong Wang, Mingzhen Xiong
{"title":"5 Gbps 0.35-/spl mu/m CMOS driver for laser diode or optical modulator","authors":"Lianming Li, Ting Huang, Jun Feng, Zhigong Wang, Mingzhen Xiong","doi":"10.1109/ESSCIR.2004.1356672","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356672","url":null,"abstract":"This paper presents a versatile driver for laser diode or optical modulator using a 0.35-/spl mu/m CMOS process. In this driver, a quasi push-pull source follower is introduced. Combined with a dynamic amplification technique, the driver's slew rate and output voltage swing are increased; meanwhile the overshoot is efficiently reduced. The driver works well at 2.5 Gbps under 3.3 V and 5 V supply voltage, consuming typical power of 310 mW and 945 mW respectively. It can give a modulation voltage (with 50-/spl Omega/ load) ranging from 0.55 V/sub P-P/ to 4.2 V/sub P-P/ under 3.3 V supply voltage and 0.6 V/sub p-p/ to 6.2 V/sub P-P/ under 5 V supply voltage, therefore it can be used as a laser diode or optical modulator driver. When the driver was tested with a LiNbO/sub 3/ modulator, clear optical eye diagrams were measured at 2.5 Gbps and 5 Gbps, respectively. The die area is 0.57 mm/sup 2/.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"24 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125673865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
2.4-GHz receiver for sensor applications 用于传感器应用的2.4 ghz接收器
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356625
Jere A. M. Järvinen, J. Kaukovuori, J. Ryynänen, J. Jussila, Kalle Kivekäs, K. Halonen
{"title":"2.4-GHz receiver for sensor applications","authors":"Jere A. M. Järvinen, J. Kaukovuori, J. Ryynänen, J. Jussila, Kalle Kivekäs, K. Halonen","doi":"10.1109/ESSCIR.2004.1356625","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356625","url":null,"abstract":"In this paper, a 3.4-mW direct-conversion receiver, operating at 2.4 GHz, is presented. The receiver includes merged low-noise amplifier and quadrature mixers, local oscillator buffers, and one analog baseband channel. The 0.13-/spl mu/m CMOS receiver consumes 2.75 mA from a 1.2-V supply. The receiver achieves 47-dB voltage gain, 28-dB NF, -21-dBm IIP3, and +18-dBm IIP2.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126162262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
A 120dB 300mW stereo audio A/D converter with 110dB THD+N 120dB 300mW立体声音频A/D转换器，110dB THD+N
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356650
P. Ammisetti, Amiya Chokhawala, Karl Thompson, J. Melanson
{"title":"A 120dB 300mW stereo audio A/D converter with 110dB THD+N","authors":"P. Ammisetti, Amiya Chokhawala, Karl Thompson, J. Melanson","doi":"10.1109/ESSCIR.2004.1356650","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356650","url":null,"abstract":"A fifth order, single-loop, multibit delta-sigma stereo audio ADC achieves 120 dB dynamic range and 110 dB THD+N while dissipating less than 300 mW of power. A feed forward path substantially reduces the signal component in the loop, enabling high dynamic range at low power levels. A second order mismatch shaper removes any nonlinearity or tones caused by element mismatch in the feedback DAC. A rough/fine input sampling scheme alleviates the loading on the input driver, improving distortion. An offset compensated switched-capacitor scheme is used in the rough buffer to avoid offset integration in AC coupled applications. Demodulation of quantization noise and delta-sigma tones is avoided by a segmented chopping technique.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133183021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
UWB considerations for "my personal global adaptive network" (MAGNET) systems “我个人的全球自适应网络”(MAGNET)系统的超宽带考虑
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-09-21 DOI: 10.1109/ESSCIR.2004.1356614
J. Gerrits, John R. Farserotu, J. Long
{"title":"UWB considerations for \"my personal global adaptive network\" (MAGNET) systems","authors":"J. Gerrits, John R. Farserotu, J. Long","doi":"10.1109/ESSCIR.2004.1356614","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356614","url":null,"abstract":"This paper outlines the role of ultrawideband (UWB) technology in the core of personal networks. An overview of existing UWB technologies is given, and two promising candidates for low data rate (1-100 kb/s) and medium data rate (100 kb/s-10 Mb/s) are treated in more detail: a time domain impulse radio approach and a novel constant envelope FM approach - UWBFM. Finally, examples of circuit implementations for impulse radio are presented.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116978003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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