Tao Chen, P. Geens, G. V. D. Plas, W. Dehaene, G. Gielen
{"title":"具有可调INL的14位130 mhz CMOS电流转向DAC","authors":"Tao Chen, P. Geens, G. V. D. Plas, W. Dehaene, G. Gielen","doi":"10.1109/ESSCIR.2004.1356644","DOIUrl":null,"url":null,"abstract":"In this paper, a 14-bit, 130-MHz CMOS current-steering DAC is presented. Different from traditional intrinsic-accuracy DACs, its INL can be improved by dynamic adjustment, which allows a significant reduction of the chip area. The layout has been carefully designed so that the signal lines of the current sources have the same length, thus good synchronization among the current sources can be achieved. The measured DNL and INL is 0.45 LSB and 0.7 LSB respectively. The spurious-free dynamic range is 82 dB at a 1 MHz signal frequency and 130 MHz sampling frequency. The DAC has been implemented in a standard 1P5M 0.25-/spl mu/m CMOS technology. The area of the current source block is 1 mm/sup 2/, and the whole core area is only 3.5 mm/sup 2/.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"30","resultStr":"{\"title\":\"A 14-bit 130-MHz CMOS current-steering DAC with adjustable INL\",\"authors\":\"Tao Chen, P. Geens, G. V. D. Plas, W. Dehaene, G. Gielen\",\"doi\":\"10.1109/ESSCIR.2004.1356644\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a 14-bit, 130-MHz CMOS current-steering DAC is presented. Different from traditional intrinsic-accuracy DACs, its INL can be improved by dynamic adjustment, which allows a significant reduction of the chip area. The layout has been carefully designed so that the signal lines of the current sources have the same length, thus good synchronization among the current sources can be achieved. The measured DNL and INL is 0.45 LSB and 0.7 LSB respectively. The spurious-free dynamic range is 82 dB at a 1 MHz signal frequency and 130 MHz sampling frequency. The DAC has been implemented in a standard 1P5M 0.25-/spl mu/m CMOS technology. The area of the current source block is 1 mm/sup 2/, and the whole core area is only 3.5 mm/sup 2/.\",\"PeriodicalId\":294077,\"journal\":{\"name\":\"Proceedings of the 30th European Solid-State Circuits Conference\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-11-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"30\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 30th European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIR.2004.1356644\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 30th European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIR.2004.1356644","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 14-bit 130-MHz CMOS current-steering DAC with adjustable INL
In this paper, a 14-bit, 130-MHz CMOS current-steering DAC is presented. Different from traditional intrinsic-accuracy DACs, its INL can be improved by dynamic adjustment, which allows a significant reduction of the chip area. The layout has been carefully designed so that the signal lines of the current sources have the same length, thus good synchronization among the current sources can be achieved. The measured DNL and INL is 0.45 LSB and 0.7 LSB respectively. The spurious-free dynamic range is 82 dB at a 1 MHz signal frequency and 130 MHz sampling frequency. The DAC has been implemented in a standard 1P5M 0.25-/spl mu/m CMOS technology. The area of the current source block is 1 mm/sup 2/, and the whole core area is only 3.5 mm/sup 2/.
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