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Proceedings of the 30th European Solid-State Circuits Conference最新文献

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A 1.35-V sense amplifier for non volatile memories based on current mode approach 基于电流模式方法的1.35 v非易失性存储器感测放大器
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356720
A. Conte, Gianbattista Lo Giudice, G. Palumbo, Alfredo Signorello
{"title":"A 1.35-V sense amplifier for non volatile memories based on current mode approach","authors":"A. Conte, Gianbattista Lo Giudice, G. Palumbo, Alfredo Signorello","doi":"10.1109/ESSCIR.2004.1356720","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356720","url":null,"abstract":"A sense amplifier for nonvolatile memories, based on a novel topology which has the benefit of a pure current mode comparison, is presented. The sense amplifier is capable of working under a very low voltage power supply - as low as 1 V, and was implemented in an EEPROM realized with a 0.18 /spl mu/m EEPROM technology. Setting the power supply at 1.65 V, experimental results shown a read access time of about 30 ns.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132717555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An inductor-based 52-GHz 0.18 /spl mu/m SiGe HBT cascode LNA with 22 dB gain 基于电感的52 ghz 0.18 /spl mu/m SiGe HBT级联放大器，增益为22 dB
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356674
M. Gordon, S. Voinigescu
{"title":"An inductor-based 52-GHz 0.18 /spl mu/m SiGe HBT cascode LNA with 22 dB gain","authors":"M. Gordon, S. Voinigescu","doi":"10.1109/ESSCIR.2004.1356674","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356674","url":null,"abstract":"A 52-GHz two-stage cascode LNA implemented in a production 0.18 /spl mu/m SiGe BiCMOS process is presented. By using inductors rather than transmission lines for matching, it occupies an area of only 200 /spl mu/m/spl times/250 /spl mu/m. The circuit features standard 60 /spl mu/m/spl times/60 /spl mu/m bond pads, on-chip bias network, and consumes 11.4 mA from a 3.3 V supply. The measured S/sub 11/ is lower than -12 dB from 35 GHz to 65 GHz and S/sub 21/ exceeds 22 dB. The gain remains above 18 dB when the supply voltage and power dissipation are reduced to 2.5 V and 19.5 mW respectively.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116982106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
A high-linear 160-MHz CMOS PGA [programmable gain amplifier] 高线性160 mhz CMOS PGA[可编程增益放大器]
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356631
B. Calvo, S. Celma, M. T. Sanz
{"title":"A high-linear 160-MHz CMOS PGA [programmable gain amplifier]","authors":"B. Calvo, S. Celma, M. T. Sanz","doi":"10.1109/ESSCIR.2004.1356631","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356631","url":null,"abstract":"This work presents the design and measurement results of a high-linearity differential programmable gain amplifier for VHF applications. Based on a new version of the degenerated differential pair, it is implemented in a 0.35 /spl mu/m CMOS technology and consumes 1.95 mW from a 3.3 V supply. The programmable gain varies from 0 to 16 dB in 4 dB steps through a 4-bit word. Experimental results show bandwidths over the 100 MHz range and total harmonic distortion figures below -60 dB.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124492758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low-power widely tunable Gm-C filter with an adaptive DC-blocking, triode-biased MOSFET transconductor 具有自适应直流阻断、三极管偏置MOSFET晶体管的低功率宽可调谐Gm-C滤波器
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356627
S. Hori, T. Maeda, N. Matsuno, H. Hida
{"title":"Low-power widely tunable Gm-C filter with an adaptive DC-blocking, triode-biased MOSFET transconductor","authors":"S. Hori, T. Maeda, N. Matsuno, H. Hida","doi":"10.1109/ESSCIR.2004.1356627","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356627","url":null,"abstract":"We propose a new transconductor to achieve a wide continuous-tuning-range filter applicable to IEEE802.11a/b/g W-LANs, W-CDMA, and Bluetooth, without sacrificing power consumption. The wide tuning range is achieved by employing triode-biased input MOSFETs, whose transconductance is widely tuned with drain bias. The transconductor also employs an adaptive DC-blocking circuit that suppresses any idle current in the high transconductance mode, resulting in minimizing the power consumption of the transconductor. A 4th-order Butterworth low-pass filter, using this new transconductor, exhibits a cutoff frequency tuning range of 0.5-12 MHz with power consumption of 1.1-4.7 mW. The tuning range is 5 times wider than other works with low power consumption.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124781498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 55
Ultra high-compliance CMOS current mirrors for low voltage charge pumps and references 用于低压电荷泵和参考的超高合规CMOS电流镜
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356659
O. Charlon, W. Redman-White
{"title":"Ultra high-compliance CMOS current mirrors for low voltage charge pumps and references","authors":"O. Charlon, W. Redman-White","doi":"10.1109/ESSCIR.2004.1356659","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356659","url":null,"abstract":"We present a study of current mirror topologies for reference sources and PLL charge pumps, where the objective is to achieve excellent input to output DC matching over almost the whole available power supply range, while maintaining a very high output resistance. From the ideal requirements, we contrast existing designs and develop new topologies which come close to the ideal in terms of available range and resistance, by using regulation at the input as well as output. We consider noise, systematic and random and matching penalties in each circuit. It is shown that mirrors operating in the triode region exhibit lower random mismatch compared with the equivalent conventional mirrors. Measured results are presented from a 0.25 /spl mu/m 2.5 V CMOS test-chip.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130513783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Adaptive threshold scheme to operate long on-chip buses at the limit of signal integrity 自适应阈值方案在信号完整性极限下运行长片上总线
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356683
A. Katoch, Manish Garg, E. Seevinck, H. Veendrick
{"title":"Adaptive threshold scheme to operate long on-chip buses at the limit of signal integrity","authors":"A. Katoch, Manish Garg, E. Seevinck, H. Veendrick","doi":"10.1109/ESSCIR.2004.1356683","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356683","url":null,"abstract":"As the technology scales, on-chip interconnects are becoming more and more narrow while their height is not scaling linearly with their width. This leads to an increase in coupling capacitance with neighbouring wires, resulting in higher crosstalk. It also leads to poor performance due to a sluggish RC response at the receiving end of the wire, which may even result in failure in (very) noisy environments. We propose an adaptive threshold scheme in which the receiver switching thresholds are adjusted according to the detected noise in the bus lines. These noise levels are dependent on both the front-end processing (transistor performance) as well as on the backend processing (metal resistance, capacitance, width and spacing). The circuit technique presented in this paper therefore automatically compensates for the process variations. This technique offers a 29% decrease of the propagation delay for a 10 mm long bus in Metal 2 in a 0.13 /spl mu/m CMOS technology in low noise conditions. The total range of control spans 75% of the bus delay.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131188107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 2.5 Gbps - 3.125 Gbps multi-core serial-link transceiver in 0.13 /spl mu/m CMOS 一个2.5 Gbps - 3.125 Gbps多核串行链路收发器，0.13 /spl mu/m CMOS
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356725
Tomas Geurts, Wim Rens, J. Crols, S. Kashiwakura, Yuichi Segawa
{"title":"A 2.5 Gbps - 3.125 Gbps multi-core serial-link transceiver in 0.13 /spl mu/m CMOS","authors":"Tomas Geurts, Wim Rens, J. Crols, S. Kashiwakura, Yuichi Segawa","doi":"10.1109/ESSCIR.2004.1356725","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356725","url":null,"abstract":"A multi-rate serdes macro that is targeting multi-channel applications has been developed in 0.13 /spl mu/m. A low-jitter LC VCO PLL can provide the master clock for up to 16 receive and transmit modules. Specific provisions for operation at different data rates are present. The receive module operates at full rate. Comma detection and 8b/10b coding are present. The transmitter has a measured output jitter of 8.1 ps rms at 2.5 Gbps. The receiver has a measured intrinsic jitter tolerance of 0.75 UI. Power consumption for the PLL is 40 mW, a receive and transmit pair consumes 100 mW.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128126403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
An area-efficient high-speed Reed-Solomon decoder in 0.25 /spl mu/m CMOS 面积高效高速里德-所罗门解码器在0.25 /spl μ m CMOS
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356723
A. Strollo, N. Petra, D. Caro, E. Napoli
{"title":"An area-efficient high-speed Reed-Solomon decoder in 0.25 /spl mu/m CMOS","authors":"A. Strollo, N. Petra, D. Caro, E. Napoli","doi":"10.1109/ESSCIR.2004.1356723","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356723","url":null,"abstract":"In this paper, a Reed-Solomon (RS) decoder for the widely used (255, 239) code is presented. The circuit exploits both a novel inversion-free Berlekamp-Massey algorithm architecture to solve the key-equation and a new bit-parallel Galois-field multiplier implementation to obtain increased circuit speed. Hardware sharing is widely used to reduce silicon area occupation. The proposed circuit, designed for a 0.25 /spl mu/m CMOS technology, compares favourably with recently proposed RS decoders.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132234292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An integrated laser radar receiver with resonance-based timing discrimination 一种基于共振时辨的集成激光雷达接收机
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356709
J. Pehkonen, J. Kostamovaara
{"title":"An integrated laser radar receiver with resonance-based timing discrimination","authors":"J. Pehkonen, J. Kostamovaara","doi":"10.1109/ESSCIR.2004.1356709","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356709","url":null,"abstract":"An integrated receiver channel for a pulsed time-of-flight laser range finder has been designed and tested. The timing discrimination is realised by converting the received unipolar pulse to a bipolar waveform immediately after the photodetector using a parallel resonant circuit. This minimises the timing errors caused by the nonlinearities of the gain blocks and a wide dynamic range can be achieved without gain control. A comparator is used to detect the timing point, i.e., the zero crossing of the bipolar pulse. The walk error of the receiver is 74 ps, or 11 mm in distance, over a dynamic range of 1:1280 using a laser pulse with half-value width of 6 ns. The minimum usable input signal is 1.9 /spl mu/A.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133806292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 /spl mu/m CMOS [ADC applications] 在0.12 /spl mu/m CMOS [ADC应用]中，1.6 GS/s, 16倍交错轨道和保持，7.6 ENOB
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356688
S. Louwsma, E. V. Tuijl, M. Vertregt, P. Scholtens, B. Nauta
{"title":"A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 /spl mu/m CMOS [ADC applications]","authors":"S. Louwsma, E. V. Tuijl, M. Vertregt, P. Scholtens, B. Nauta","doi":"10.1109/ESSCIR.2004.1356688","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356688","url":null,"abstract":"A 1.6 GS/s track and hold circuit that produces 16 interleaving, 100 MS/s voltage buffered output signals is presented. The achieved SFDR for a 950 MHz full scale input signal is 50 dB. Phase alignment is better than 2 ps and aperture uncertainty is less than 0.8 ps (RMS). The chip includes two analog to digital converters and a switching matrix to accommodate measurement of all sampled output signals and their timing relation. Chip area is 0.14 mm/sup 2/, excluding the AD converters. The chip is made in a 0.12 /spl mu/m, 1.2 V CMOS process. Power consumption of the interleaving T/H circuit is 32 mW.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115312617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
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