高线性160 mhz CMOS PGA[可编程增益放大器]

Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI:10.1109/ESSCIR.2004.1356631

B. Calvo, S. Celma, M. T. Sanz

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摘要

本文介绍了一种用于甚高频应用的高线性差分可编程增益放大器的设计和测量结果。它基于新版本的退化差分对，采用0.35 /spl mu/m CMOS技术实现，从3.3 V电源消耗1.95 mW。可编程增益通过4位字以4 dB步长从0到16 dB变化。实验结果表明，带宽超过100 MHz，总谐波失真值低于-60 dB。

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A high-linear 160-MHz CMOS PGA [programmable gain amplifier]

This work presents the design and measurement results of a high-linearity differential programmable gain amplifier for VHF applications. Based on a new version of the degenerated differential pair, it is implemented in a 0.35 /spl mu/m CMOS technology and consumes 1.95 mW from a 3.3 V supply. The programmable gain varies from 0 to 16 dB in 4 dB steps through a 4-bit word. Experimental results show bandwidths over the 100 MHz range and total harmonic distortion figures below -60 dB.

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Proceedings of the 30th European Solid-State Circuits Conference

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