{"title":"基于电感的52 ghz 0.18 /spl mu/m SiGe HBT级联放大器，增益为22 dB","authors":"M. Gordon, S. Voinigescu","doi":"10.1109/ESSCIR.2004.1356674","DOIUrl":null,"url":null,"abstract":"A 52-GHz two-stage cascode LNA implemented in a production 0.18 /spl mu/m SiGe BiCMOS process is presented. By using inductors rather than transmission lines for matching, it occupies an area of only 200 /spl mu/m/spl times/250 /spl mu/m. The circuit features standard 60 /spl mu/m/spl times/60 /spl mu/m bond pads, on-chip bias network, and consumes 11.4 mA from a 3.3 V supply. The measured S/sub 11/ is lower than -12 dB from 35 GHz to 65 GHz and S/sub 21/ exceeds 22 dB. The gain remains above 18 dB when the supply voltage and power dissipation are reduced to 2.5 V and 19.5 mW respectively.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"30","resultStr":"{\"title\":\"An inductor-based 52-GHz 0.18 /spl mu/m SiGe HBT cascode LNA with 22 dB gain\",\"authors\":\"M. Gordon, S. Voinigescu\",\"doi\":\"10.1109/ESSCIR.2004.1356674\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 52-GHz two-stage cascode LNA implemented in a production 0.18 /spl mu/m SiGe BiCMOS process is presented. By using inductors rather than transmission lines for matching, it occupies an area of only 200 /spl mu/m/spl times/250 /spl mu/m. The circuit features standard 60 /spl mu/m/spl times/60 /spl mu/m bond pads, on-chip bias network, and consumes 11.4 mA from a 3.3 V supply. The measured S/sub 11/ is lower than -12 dB from 35 GHz to 65 GHz and S/sub 21/ exceeds 22 dB. The gain remains above 18 dB when the supply voltage and power dissipation are reduced to 2.5 V and 19.5 mW respectively.\",\"PeriodicalId\":294077,\"journal\":{\"name\":\"Proceedings of the 30th European Solid-State Circuits Conference\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-11-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"30\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 30th European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIR.2004.1356674\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 30th European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIR.2004.1356674","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An inductor-based 52-GHz 0.18 /spl mu/m SiGe HBT cascode LNA with 22 dB gain
A 52-GHz two-stage cascode LNA implemented in a production 0.18 /spl mu/m SiGe BiCMOS process is presented. By using inductors rather than transmission lines for matching, it occupies an area of only 200 /spl mu/m/spl times/250 /spl mu/m. The circuit features standard 60 /spl mu/m/spl times/60 /spl mu/m bond pads, on-chip bias network, and consumes 11.4 mA from a 3.3 V supply. The measured S/sub 11/ is lower than -12 dB from 35 GHz to 65 GHz and S/sub 21/ exceeds 22 dB. The gain remains above 18 dB when the supply voltage and power dissipation are reduced to 2.5 V and 19.5 mW respectively.
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