Adaptive threshold scheme to operate long on-chip buses at the limit of signal integrity

As the technology scales, on-chip interconnects are becoming more and more narrow while their height is not scaling linearly with their width. This leads to an increase in coupling capacitance with neighbouring wires, resulting in higher crosstalk. It also leads to poor performance due to a sluggish RC response at the receiving end of the wire, which may even result in failure in (very) noisy environments. We propose an adaptive threshold scheme in which the receiver switching thresholds are adjusted according to the detected noise in the bus lines. These noise levels are dependent on both the front-end processing (transistor performance) as well as on the backend processing (metal resistance, capacitance, width and spacing). The circuit technique presented in this paper therefore automatically compensates for the process variations. This technique offers a 29% decrease of the propagation delay for a 10 mm long bus in Metal 2 in a 0.13 /spl mu/m CMOS technology in low noise conditions. The total range of control spans 75% of the bus delay.