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Proceedings of the 30th European Solid-State Circuits Conference最新文献

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An EMC-robust high voltage system-on-chip 一个具有emc鲁棒性的高压片上系统
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356714
L. V. Voorde, K. Appeltans, J. Alonso
{"title":"An EMC-robust high voltage system-on-chip","authors":"L. V. Voorde, K. Appeltans, J. Alonso","doi":"10.1109/ESSCIR.2004.1356714","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356714","url":null,"abstract":"This paper describes an intelligent actuator and sensor interface for a bridge-type sensor for automotive applications, requiring high voltage capability, robustness for electrostatic discharge (ESD) and electromagnetic compatibility (EMC) and having to operate in a wide temperature range. With respect to EMC, both low emission as well as low sensitivity to external disturbances is required. In this paper the main functional blocks of the sensor are described with emphasis on the special circuits to fulfil the automotive requirements.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132333233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A mixed-signal chip with HV-protected pins in 0.35-/spl mu/m-based HV-technology 一种混合信号芯片，采用基于0.35 /spl mu/m高压技术的高压保护引脚
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356699
Wim Van de Maele, F. Stevens, A. Huot-Marchand, B. Sekerkiran
{"title":"A mixed-signal chip with HV-protected pins in 0.35-/spl mu/m-based HV-technology","authors":"Wim Van de Maele, F. Stevens, A. Huot-Marchand, B. Sekerkiran","doi":"10.1109/ESSCIR.2004.1356699","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356699","url":null,"abstract":"This paper describes a mixed digital-analog high-voltage ASIC. Designed in a 0.35 /spl mu/m based high-voltage technology, it has integrated a large set of functions ranging from switched mode power supplies, low drop regulators and switchable supplies, over precision ADC and monitoring functions, to high speed data processing and communication. The circuit is operated in a harsh environment, which causes short circuits of several pins to the ground or to the HV supply up to 60 V. Besides the new solutions for common circuits to come to an area-efficient power-critical implementation of the customer's specifications, a lot of attention had to be paid to these short circuits.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128127448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low jitter triple-band digital LC PLL in 130nm CMOS 低抖动三波段数字LC锁相环在130nm CMOS
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356695
N. D. Dalt, E. Thaller, P. Gregorius, L. Gazsi
{"title":"A low jitter triple-band digital LC PLL in 130nm CMOS","authors":"N. D. Dalt, E. Thaller, P. Gregorius, L. Gazsi","doi":"10.1109/ESSCIR.2004.1356695","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356695","url":null,"abstract":"A fully integrated digital LC PLL for low jitter frequency synthesis in a standard digital 130 nm CMOS technology is presented. The PLL features a fully digital core and a digitally controlled LC oscillator. It supports triple-band operation in multi-GHz range (2.1 GHz, 3.3 GHz and 4.4 GHz) with a single programmable coil, resulting in a die area as small as 0.24 mm/sup 2/. While consuming 16 mA of current, the PLL achieves an outstanding long-term jitter of 640 fs, which compares with the most advanced analog PLLs. Its digital nature makes it easily implementable in the main stream digital CMOS technologies, robust against noise and thus ideal for application as a low jitter clock multiplying unit in digital intensive systems on chip (SoCs).","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134396201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A 48-860 MHz TV splitter amplifier exhibiting an IIP2 and IIP3 of 94dBmV and 73dBmV 48- 860mhz电视分频放大器，IIP2和IIP3分别为94dBmV和73dBmV
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356651
J. V. Sinderen, M. Notten, E. Stikvoort, F. Seneschal
{"title":"A 48-860 MHz TV splitter amplifier exhibiting an IIP2 and IIP3 of 94dBmV and 73dBmV","authors":"J. V. Sinderen, M. Notten, E. Stikvoort, F. Seneschal","doi":"10.1109/ESSCIR.2004.1356651","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356651","url":null,"abstract":"This paper describes a 48-860 MHz TV splitter amplifier with three outputs, based on a negative feedback design. The amplifier is intended for TV, VCR and set-top box (STB) applications, where multiple tuners have to be connected to the same cable outlet. The amplifier compromises high linearity and low noise figure by controlling its gain. At a frequency of 850 MHz, the input IP2 and IP3 are 94 dBmV and 73 dBmV, respectively, for the lowest gain setting while the noise figure is 7 dB for the highest gain setting. The design is fabricated in a 0.5 /spl mu/m, 30 GHz BiCMOS technology and dissipates 130 mW from a 3.3 V supply.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124033252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
L1/L2 dual-band CMOS GPS receiver L1/L2双频CMOS GPS接收机
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356624
Jongmoon Kim, Sang-Bock Cho, J. Ko
{"title":"L1/L2 dual-band CMOS GPS receiver","authors":"Jongmoon Kim, Sang-Bock Cho, J. Ko","doi":"10.1109/ESSCIR.2004.1356624","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356624","url":null,"abstract":"This paper presents the design and implementation of an L1/L2 dual-band global positioning system (GPS) receiver. The receiver has been implemented in a 1P6M 0.18 /spl mu/m CMOS technology. It consists of a low-noise pre-amplifier, I-Q mixers, VGA-merged complex BPFs, 2-bit analog-digital converters, and a whole phase-locked loop synthesizer, excluding loop filter. The measured results show 95-dB maximum gain, 8.5-dB noise figure and -31-dBm IIP3 while consuming 10.6 mA from a 1.8 V supply voltage.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124092773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A harmonic quadrature LO generator using a 90/spl deg/ delay-locked loop [zero-IF transceiver applications] 一种使用90/spl度/锁滞环的谐波正交本振发生器[零中频收发器应用]
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356634
J. Craninckx, V. Gravot, S. Donnay
{"title":"A harmonic quadrature LO generator using a 90/spl deg/ delay-locked loop [zero-IF transceiver applications]","authors":"J. Craninckx, V. Gravot, S. Donnay","doi":"10.1109/ESSCIR.2004.1356634","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356634","url":null,"abstract":"To overcome problems with DC-offsets and LO pulling in zero-IF transceivers, a technique is presented to generate quadrature LO signals from an oscillator signal that is the N-th subharmonic of the desired RF frequency. A delay-locked loop is used to generate a set of LO signals that are spaced 90/spl deg//N apart. These can be applied directly to a harmonic mixer, or combined into quadrature LO signals for a standard mixer. A prototype implementation generates quadrature LO signals for a direct-conversion 5 GHz WLAN mixer from a half-frequency VCO in a 0.35 /spl mu/m BiCMOS process. The current consumption is 9 mA and die area is 0.12 mm/sup 2/.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115572673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell sub- 100nm PD/SOI CMOS SRAM电池的变异性分析
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356655
R. Joshi, S. Mukhopadhyay, D. Plass, Y. Chan, C. Chuang, A. Devgan
{"title":"Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell","authors":"R. Joshi, S. Mukhopadhyay, D. Plass, Y. Chan, C. Chuang, A. Devgan","doi":"10.1109/ESSCIR.2004.1356655","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356655","url":null,"abstract":"We have studied the impacts of floating body effect, device leakage, and gate oxide tunneling leakage on the read and write stability of a PD/SOI CMOS SRAM cell under Vt, L and W variations in sub-100 nm technology for the first time. The floating body effect is shown to degrade the read stability while improving the write stability. On the other hand, the gate-to-body tunneling current improves the read stability while degrading the write stability. It is also shown that the use of high-Vt cell transistors can improve the read and write stability without causing significant performance degradation.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125807679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
Performance degradation of an LC-tank VCO by impact of digital switching noise 数字开关噪声对LC-tank压控振荡器性能的影响
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356632
C. Soens, G. V. D. Plas, P. Wambacq, S. Donnay
{"title":"Performance degradation of an LC-tank VCO by impact of digital switching noise","authors":"C. Soens, G. V. D. Plas, P. Wambacq, S. Donnay","doi":"10.1109/ESSCIR.2004.1356632","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356632","url":null,"abstract":"In mixed-signal designs, digital switching noise is an important limitation for the analog and RF performance. This paper reports a thorough experimental and analytical study of the impact of digital switching noise on a 3.5 GHz LC-tank voltage controlled oscillator (VCO) in 0.18 /spl mu/m CMOS. Frequency modulation is recognized as the dominating mechanism behind the impact of digital switching noise in the investigated frequency range (DC to 15 MHz). The dominating coupling path, from the source of noise to the VCO, in this frequency range is via the non-ideal metal ground lines.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125234569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
High-bit-rate low-power decision circuit using InP/InGaAs HBT technology [master-slave D-type flip-flop] 采用InP/InGaAs HBT技术的高比特率低功耗决策电路[主从d型触发器]
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356691
K. Ishii, H. Nosaka, M. Ida, K. Kurishima, M. Hirata, Takatorno Enoki, Tsugumichi Shibata
{"title":"High-bit-rate low-power decision circuit using InP/InGaAs HBT technology [master-slave D-type flip-flop]","authors":"K. Ishii, H. Nosaka, M. Ida, K. Kurishima, M. Hirata, Takatorno Enoki, Tsugumichi Shibata","doi":"10.1109/ESSCIR.2004.1356691","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356691","url":null,"abstract":"We have designed and fabricated a high-bit-rate low-power decision circuit using InP/InGaAs heterojunction bipolar transistors (HBTs) with a cutoff frequency f/sub T/ of approximately 150 GHz and a maximum oscillation frequency f/sub max/ of approximately 200 GHz. A novel master-slave D-type flip-flop (MS-DFF) circuit was used as the decision core circuit. The decision circuit operates approximately 15% faster than one with a conventional MS-DFF core. We achieved error-free operation at a data rate of up to 60 Gbit/s for the first time. The power consumption was only approximately 0.7 W, including that of the clock, data, and output buffers.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123333754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 5.0mW 0dBm FSK transmitter for 315/433 MHz ISM applications in 0.25 /spl mu/m CMOS 用于315/433 MHz ISM应用的5.0mW 0dBm FSK发射机，采用0.25 /spl mu/m CMOS
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356652
N. Boom, Wim Rens, J. Crols
{"title":"A 5.0mW 0dBm FSK transmitter for 315/433 MHz ISM applications in 0.25 /spl mu/m CMOS","authors":"N. Boom, Wim Rens, J. Crols","doi":"10.1109/ESSCIR.2004.1356652","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356652","url":null,"abstract":"An ultra-low power multi-channel narrowband FSK transmitter has been developed that operates in the 315/433 MHz bands for ISM applications and consumes only 5.0 mW at 1.3 V for an output power of 0 dBm. For an output power of -10 dBm the combination of the minimum power supply (0.9 V) and maximal data rate (100 kbps) leads to an energy consumption of less than 17 nJ/bit. The transmitter has a direct PLL modulation architecture using a /spl Delta//spl Sigma/ fractional-N synthesizer. The IC is implemented in a 0.25 /spl mu/m CMOS process and occupies 4.8 mm/sup 2/.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124626536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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