L1/L2 dual-band CMOS GPS receiver

Abstract

This paper presents the design and implementation of an L1/L2 dual-band global positioning system (GPS) receiver. The receiver has been implemented in a 1P6M 0.18 /spl mu/m CMOS technology. It consists of a low-noise pre-amplifier, I-Q mixers, VGA-merged complex BPFs, 2-bit analog-digital converters, and a whole phase-locked loop synthesizer, excluding loop filter. The measured results show 95-dB maximum gain, 8.5-dB noise figure and -31-dBm IIP3 while consuming 10.6 mA from a 1.8 V supply voltage.