K. Ishii, H. Nosaka, M. Ida, K. Kurishima, M. Hirata, Takatorno Enoki, Tsugumichi Shibata
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We have designed and fabricated a high-bit-rate low-power decision circuit using InP/InGaAs heterojunction bipolar transistors (HBTs) with a cutoff frequency f/sub T/ of approximately 150 GHz and a maximum oscillation frequency f/sub max/ of approximately 200 GHz. A novel master-slave D-type flip-flop (MS-DFF) circuit was used as the decision core circuit. The decision circuit operates approximately 15% faster than one with a conventional MS-DFF core. We achieved error-free operation at a data rate of up to 60 Gbit/s for the first time. The power consumption was only approximately 0.7 W, including that of the clock, data, and output buffers.
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