{"title":"Technology considerations for automotive [automotive electronics]","authors":"H. Casier, P. Moens, Koen Appeltans","doi":"10.1109/ESSCIR.2004.1356610","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356610","url":null,"abstract":"In this paper, the evolution of automotive electronics and the specific electronic requirements posed by the automotive environment are discussed. Safety is a very dominant factor in automotive applications and this has a large impact on the required robustness of the electronics. As an example, DMOS optimization and ESD robustness considerations have led to the N-epi based structure of the AMIS 13T automotive technology. On top of the robust technology, innovative design techniques are described which further improve the robustness of the high voltage smart power applications for the harsh environment of the automotive electronics.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"65 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133877048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Marco Giardina, A. Stek, G. D. Jong, J. Bergervoet
{"title":"Design of low noise CMOS OEIC for blu-ray disc optical storage systems","authors":"Marco Giardina, A. Stek, G. D. Jong, J. Bergervoet","doi":"10.1109/ESSCIR.2004.1356670","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356670","url":null,"abstract":"This paper discusses the design of an optoelectronic integrated circuit (OEIC intended for optical recording systems. The electronic noise in the system is an issue for high-speed operation and dual-layer blu-ray discs. In order to get a good impression of the various noise sources in the system, a noise calculation model has been developed. The design of the photo-diode and the preamplifiers in a BiCMOS/CMOS processes is discussed. The advantage of CMOS downscaling on the speed race is reported. A novel low-noise, low-voltage and low-power CMOS topology is described. Furthermore, some preliminary results of a test OEIC in 0.18 /spl mu/m CMOS are also reported. The measured input-referred current noise is 350 fAHz/sup -1/2/ at 20 MHz equivalent with the shot-noise level generated by a photo current of 380 nA. The active area of the test die, excluding bonding pads, is 0.36/spl times/0.26 mm/sup 2/ and the power consumption is 12.5 mW from a 1.5 V supply voltage at room temperature.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122105412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Oh, Quan Le, Sang-Gug Lee, N.D.B. Yen, Ho-Yong Kang, T. Yoo
{"title":"Burst-mode transmitter for 1.25Gb/s Ethernet PON applications [passive optical networks]","authors":"Y. Oh, Quan Le, Sang-Gug Lee, N.D.B. Yen, Ho-Yong Kang, T. Yoo","doi":"10.1109/ESSCIR.2004.1356673","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356673","url":null,"abstract":"This paper presents a burst-mode 1.25 Gb/s transmitter, suitable for use in Ethernet PON (E-PON) applications. With a burst enable signal, the transmitter proposed in this paper allows fast responses from the beginning of high-speed burst data while a conventional automatic power control circuit, based on feedback from a monitor photodiode, was used. The chip was implemented in 0.18 /spl mu/m CMOS technology and occupies an area of 0.9/spl times/0.75 mm/sup 2/ with about 260 mW power dissipation under 3.3 V supply. Measurements show a stable transmitted optical power over a wide temperature range (-40/spl deg/C to 80/spl deg/C) with above 10 dB extinction ratio.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124991641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 5.2-GHz silicon bipolar power amplifier for IEEE 802.11a and HIPERLAN2 wireless LANs","authors":"A. Scuderi, F. Carrara, Guiseppe Palmisano","doi":"10.1109/ESSCIR.2004.1356653","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356653","url":null,"abstract":"A monolithic 5.2-GHz linear power amplifier for IEEE802.11a and HIPERLAN2 wireless local area networks was integrated using a low-cost 46-GHz-f/sub T/ silicon bipolar process. At a 3-V supply voltage, the circuit exhibits a 25-dBm saturated output power, 26% maximum power-added efficiency, and 23.5-dBm output 1-dB compression point. The small-signal gain is 24 dB. Thanks to a linearizing bias network, the power amplifier is able to comply with the stringent error vector magnitude requirements of the standard up to a 19-dBm output power level. The device also features a power control function with a high dynamic range of 40 dB.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125571124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Antonio Lopez-Martin, S. Baswa, Jaime Ramírez-Angulo, R. Carvajal
{"title":"Power-efficient super class AB OTAs","authors":"Antonio Lopez-Martin, S. Baswa, Jaime Ramírez-Angulo, R. Carvajal","doi":"10.1109/ESSCIR.2004.1356660","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356660","url":null,"abstract":"A family of low-voltage power-efficient class AB CMOS operational transconductance amplifiers (OTAs) is described. It is based on the combination of adaptive biasing techniques and resistive local common-mode feedback (LCMFB), which provides increased dynamic current boosting and gain-bandwidth product (GBW). The different classes of AB OTA topologies presented result from the combination of various adaptive biasing schemes and LCMFB. A 0.5-/spl mu/m CMOS implementation of three different OTAs shows enhancement factors of slew-rate and GBW up to 280 and 3.6, respectively, for an 80-pF load, compared to a conventional class A OTA with the same quiescent currents and supply voltage. The overhead in area, noise, and static power consumption, is minimal.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125945626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Two high-speed optical front-ends with integrated photodiodes in standard 0.18 /spl mu/m CMOS","authors":"C. Hermans, P. Leroux, M. Steyaert","doi":"10.1109/ESSCIR.2004.1356671","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356671","url":null,"abstract":"Two optical front-ends implemented in a standard 0.18 /spl mu/m CMOS technology are presented. They differ mainly in layout topology of the photodiode. The front-end with classical n-well diode achieves a bitrate of 300 Mbit/s. At an input power of -8 dBm, the BER is 2/spl times/10/sup -10/. The front-end with differential n-well diode outperforms the classical n-well topology and reaches bitrates up to 500 Mbit/s. At this speed, an input power of -8 dBm is sufficient to have a BER of 3/spl times/10/sup -10/. Both front-ends consume only 17 mW.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121146332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A wideband CMOS VCO for zero-IF GSM-CDMA single-chip transceiver","authors":"Kostas Manetakis, D. Jessie, C. Narathong","doi":"10.1109/ESSCIR.2004.1356637","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356637","url":null,"abstract":"This paper presents a low-power CMOS VCO in a 0.35 /spl mu/m process which achieves a tuning range of 2.47 GHz-3.47 GHz and phase noise performance of -145dBc/Hz at 3 MHz offset (from a 1.8 GHz carrier). 5-bit digital coarse-tuning and accumulation-type MOS varactors allow for a 33% tuning range, which is required to cover the LO frequency range of a zero-IF GSM-CDMA transceiver and to account for process and temperature variations. Optimum design techniques ensure low VCO gain (<104 MHz/V) for good interoperability with the frequency synthesizer. An integrated regulator provides low supply pushing (40 kHz/V) and reduces the AM-to-PM sensitivity from the supply.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123931319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
X. Duo, Tommi Torikka, Lirong Zheng, M. Ismail, H. Tenhunen
{"title":"On-chip versus off-chip passives in multi-band radio design","authors":"X. Duo, Tommi Torikka, Lirong Zheng, M. Ismail, H. Tenhunen","doi":"10.1109/ESSCIR.2004.1356684","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356684","url":null,"abstract":"This paper presents on-chip versus off-chip passives in multi-band radio design. The analysis is demonstrated through several multi-band low noise amplifiers designs in SiGe BiCMOS and GaAs PHEMT. Cost-performance trade-off analysis shows that when on-chip passives are moved off chip, performance of RF circuits is always improved. However, simple RF circuits do not show obvious cost-benefits, whereas complex RF circuits such as multi-band radio can have significant cost savings by using off-chip passives.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115347841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"LC-oscillators above 100 GHz in silicon-based technology","authors":"W. Winkler, J. Borngräber, B. Heinemann","doi":"10.1109/ESSCIR.2004.1356635","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356635","url":null,"abstract":"In this paper, voltage-controlled LC-oscillators (VCO) are presented, reaching oscillation frequencies well above 100 GHz. The oscillators were fabricated in a 200 GHz SiGe:C BiCMOS technology with 0.25 /spl mu/m minimum feature size. In the design of the VCOs, two approaches for the frequency tuning of the oscillators were investigated. In the first design, the current flowing through the oscillator core was varied to get control of the output frequency. In the second design, a MOS-type varicap was used to tune the frequency of the LC-oscillator. The fabricated oscillators have a tuning range from 105.8 GHz to 114.5 GHz and from 113.2 GHz to 117.2 GHz, respectively.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124060187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Winkler, J. Borngräber, H. Gustat, F. Korndörfer
{"title":"60 GHz transceiver circuits in SiGe:C BiCMOS technology","authors":"W. Winkler, J. Borngräber, H. Gustat, F. Korndörfer","doi":"10.1109/ESSCIR.2004.1356623","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356623","url":null,"abstract":"This paper presents the design and measurement of key circuit building blocks for a high-data-rate transceiver in the 60 GHz band. The adopted modulation scheme is ASK, for a simple configuration with high data rate. The circuits presented are: LNA, oscillator, mixer, modulator and demodulator. The circuits are fabricated in a 0.25 /spl mu/m SiGe:C BiCMOS technology.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121589339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}